1 ;/*******************************************************************************
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3 ;* This software is supplied by Renesas Electronics Corporation and is only
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4 ;* intended for use with Renesas products. No other uses are authorized. This
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5 ;* software is owned by Renesas Electronics Corporation and is protected under
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6 ;* all applicable laws, including copyright laws.
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7 ;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 ;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 ;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 ;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 ;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 ;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 ;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 ;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 ;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 ;* Renesas reserves the right, without notice, to make changes to this software
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17 ;* and to discontinue the availability of this software. By using this software,
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18 ;* you agree to the additional terms and conditions found by accessing the
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20 ;* http://www.renesas.com/disclaimer
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22 ;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.
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23 ;*******************************************************************************/
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24 ;/*******************************************************************************
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25 ;* File Name : vbar_init.s
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27 ;* Device(s) : Aragon
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28 ;* Tool-Chain : DS-5 Ver 5.8
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31 ;* H/W Platform : Aragon CPU Board
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32 ;* Description : Aragon Sample Program
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33 ;*******************************************************************************/
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34 ;/*******************************************************************************
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35 ;* History : DD.MM.YYYY Version Description
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36 ;* : 23.05.2012 0.01
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37 ;*******************************************************************************/
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39 ;==================================================================
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40 ; This code provides basic global enable for Cortex-A9 cache.
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41 ; It also enables branch prediction
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42 ; This code must be run from a privileged mode
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43 ;==================================================================
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44 AREA INIT_VBAR, CODE, READONLY
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46 IMPORT ||Image$$VECTOR_MIRROR_TABLE$$Base||
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47 ; IMPORT ||Image$$VECTOR_TABLE$$Base||
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53 ;===================================================================
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54 ; Set Vector Base Address Register (VBAR) to point to this application's vector table
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55 ;===================================================================
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56 LDR r0, =||Image$$VECTOR_MIRROR_TABLE$$Base||
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57 ; LDR r0, =||Image$$VECTOR_TABLE$$Base||
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58 MCR p15, 0, r0, c12, c0, 0
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60 ;===================================================================
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62 ;===================================================================
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64 MRC p15, 0, r0, c1, c0, 0 ;/* Read CP15 System Control register (SCTLR) */
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65 BIC r0, r0, #(0x1 << 13) ;/* Clear V bit 13 to set Low Vectors */
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66 MCR p15, 0, r0, c1, c0, 0 ;/* Write CP15 System Control register */
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