git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_RZ_R7S72100_IAR_DS-5/Source/RenesasFiles/include/iodefines/ostm_iodefine.h

   1 /*******************************************************************************\r
   2 * DISCLAIMER\r
   3 * This software is supplied by Renesas Electronics Corporation and is only\r
   4 * intended for use with Renesas products. No other uses are authorized. This\r
   5 * software is owned by Renesas Electronics Corporation and is protected under\r
   6 * all applicable laws, including copyright laws.\r
   7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
   8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
   9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
  10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
  11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
  12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
  13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
  14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
  15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
  16 * Renesas reserves the right, without notice, to make changes to this software\r
  17 * and to discontinue the availability of this software. By using this software,\r
  18 * you agree to the additional terms and conditions found by accessing the\r
  19 * following link:\r
  20 * http://www.renesas.com/disclaimer\r
  21 *\r
  22 * Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved.\r
  23 *******************************************************************************/\r
  24 /*******************************************************************************\r
  25 * File Name     : ostm_iodefine.h\r
  26 * Version       : 0.01\r
  27 * Device(s)     : Aragon\r
  28 * Tool-Chain    : DS-5 Ver 5.8\r
  29 *                 ARM Complier \r
  30 *               : \r
  31 * H/W Platform  : Aragon CPU Board\r
  32 * Description   : Aragon Sample Program vecotr.s\r
  33 *******************************************************************************/\r
  34 /*******************************************************************************\r
  35 * History : DD.MM.YYYY Version Description\r
  36 *         : 27.07.2012 0.01             \8eQ\8dl\8e\91\97¿\81Fsec11_OSTM_120601.pdf\r
  37 *******************************************************************************/\r
  38 #ifndef __OSTM_IODEFINE_H__\r
  39 #define __OSTM_IODEFINE_H__\r
  40 \r
  41 #include "typedefine.h"\r
  42 \r
  43 struct st_ostm_n {                              /* struct OSTM  */\r
  44        _UDWORD OSTMnCMP;                        /* OSTMnCMP     */\r
  45        _UDWORD OSTMnCNT;                        /* OSTMnCNT     */\r
  46        _UBYTE wk0[8];                           /*              */\r
  47        union {                                  /* OSTMnTE      */\r
  48              _UBYTE BYTE;                       /*  Byte Access */\r
  49              struct {                           /*  Bit Access  */\r
  50                     _UBYTE OSTMnTE:1;           /*   OSTMnTE    */\r
  51                     _UBYTE :7;                  /*              */\r
  52                     } BIT;                      /*              */\r
  53              } OSTMnTE;                         /*              */\r
  54        _UBYTE wk1[3];                           /*              */\r
  55        union {                                  /* OSTMnTS      */\r
  56              _UBYTE BYTE;                       /*  Byte Access */\r
  57              struct {                           /*  Bit Access  */\r
  58                     _UBYTE OSTMnTS:1;           /*   OSTMnTS    */\r
  59                     _UBYTE :7;                  /*              */\r
  60                     } BIT;                      /*              */\r
  61              } OSTMnTS;                         /*              */\r
  62        _UBYTE wk2[3];                           /*              */\r
  63        union {                                  /* OSTMnTT      */\r
  64              _UBYTE BYTE;                       /*  Byte Access */\r
  65              struct {                           /*  Bit Access  */\r
  66                     _UBYTE OSTMnTT:1;           /*   OSTMnTT    */\r
  67                     _UBYTE :7;                  /*              */\r
  68                     } BIT;                      /*              */\r
  69              } OSTMnTT;                         /*              */\r
  70        _UBYTE wk3[7];                           /*              */\r
  71        union {                                  /* OSTMnCTL     */\r
  72              _UBYTE BYTE;                       /*  Byte Access */\r
  73              struct {                           /*  Bit Access  */\r
  74                     _UBYTE OSTMnMD0:1;          /*   OSTMnMD0   */\r
  75                     _UBYTE OSTMnMD1:1;          /*   OSTMnMD1   */\r
  76                     _UBYTE :6;                  /*              */\r
  77                     } BIT;                      /*              */\r
  78              } OSTMnCTL;                        /*              */\r
  79 };                                              /*              */\r
  80 \r
  81 #define OSTM0           (*(volatile struct st_ostm_n *)0xFCFEC000)   /* OSTM0 Address */\r
  82 #define OSTM1           (*(volatile struct st_ostm_n *)0xFCFEC400)   /* OSTM1 Address */\r
  83 \r
  84 \r
  85 #endif /* __OSTM_IODEFINE_H__ */\r
  86 \r
  87 /* End of File */\r