6 memory S:0x00000000 S:0x07ffffff ro
\r
7 memory S:0x08000000 S:0x0fffffff cache
\r
8 memory S:0x3fffff80 S:0x3fffffff nocache noverify
\r
9 memory S:0xfcfe0000 S:0xfcfeffff nocache noverify
\r
11 # USB Register accessed by only 16bit
\r
12 memory S:0xe8010000 S:0xe801010f 16
\r
13 memory S:0xe8207000 S:0xe820710f 16
\r
16 ######################################
\r
17 # Release L2 cache standby ##
\r
18 ######################################
\r
19 mem set 0x3fffff80 32 0x00000001
\r
21 # ;*Writing to On-Chip Data-Retention RAM is enabled.
\r
22 # ;SYSCR3.RRAMWE3=RRAMWE2=RRAMWE1=RRAMWE0=1
\r
23 memory set S:0xFCFE0408 0 {(unsigned char)0x0F}
\r
26 ######################################
\r
27 # CS0 Port Setting ##
\r
28 # CS1 Port Setting ##
\r
29 ######################################
\r
30 # P9_1(A25), P9_0(A24),
\r
31 mem set 0xfcfe3424 16 0x0003 # PMC9
\r
32 mem set 0xfcfe3A24 16 0x0000 # PFCAE9
\r
33 mem set 0xfcfe3624 16 0x0000 # PFCE9
\r
34 mem set 0xfcfe3524 16 0x0000 # PFC9
\r
35 mem set 0xfcfe7224 16 0x0003 # PIPC9
\r
36 # P8_15(A23), P8_14(A22), P8_13(A21),
\r
37 mem set 0xfcfe3420 16 0xffff # PMC8
\r
38 mem set 0xfcfe3A20 16 0x0000 # PFCAE8
\r
39 mem set 0xfcfe3620 16 0x0000 # PFCE8
\r
40 mem set 0xfcfe3520 16 0x0000 # PFC8
\r
41 mem set 0xfcfe7220 16 0xffff # PIPC8
\r
43 mem set 0xfcfe340c 16 0x0080 # PMC3
\r
44 mem set 0xfcfe3A0c 16 0x0080 # PFCAE3
\r
45 mem set 0xfcfe360c 16 0x0080 # PFCE3
\r
46 mem set 0xfcfe350c 16 0x0000 # PFC3
\r
47 mem set 0xfcfe720c 16 0x0080 # PIPC3
\r
49 # SRSR - SDRAM Setup?
\r
50 # P7_8(RD#), P7_7(WE1#), P7_6(WE0#), P7_5(RD/WR#), P7_4(CKE), P7_3(CAS#), P7_2(RAS#), P7_1(CS3#), P7_0(CS0#)
\r
51 mem set 0xfcfe341c 16 0xffff # PMC7
\r
52 mem set 0xfcfe3A1c 16 0x0000 # PFCAE7
\r
53 mem set 0xfcfe361c 16 0x0000 # PFCE7
\r
54 mem set 0xfcfe351c 16 0x0000 # PFC7
\r
55 mem set 0xfcfe721c 16 0xffff # PIPC7
\r
57 mem set 0xfcfe3414 16 0x0100 # PMC5
\r
58 mem set 0xfcfe3A14 16 0x0100 # PFCAE5
\r
59 mem set 0xfcfe3614 16 0x0000 # PFCE5
\r
60 mem set 0xfcfe3514 16 0x0100 # PFC5
\r
61 mem set 0xfcfe7214 16 0x0100 # PIPC5
\r
63 # disable verify on SDRAM setup registers
\r
64 memory S:0x3fffc000 S:0x3fffffff nocache noverify
\r
66 ######################################
\r
67 # CS2 SDRAM Setting ##
\r
68 ######################################
\r
69 mem set 0x3fffc00c 32 0x00004C00 # CS2BCR - SDRAM
\r
70 mem set 0x3fffc030 32 0x00000080 # CS2WCR - SDRAM
\r
71 mem set 0x3fffd040 16 0x0000 # SDRAM_MODE_CS2
\r
73 ######################################
\r
74 # CS3 SDRAM Setting ##
\r
75 ######################################
\r
77 mem set 0x3fffc010 32 0x00004C00 # CS3BCR - SDRAM
\r
78 mem set 0x3fffc034 32 0x00002492 # CS3WCR - SDRAM
\r
79 mem set 0x3fffc04c 32 0x00120812 # SDCR
\r
80 mem set 0x3fffc058 32 0xA55A0020 # RTCOR
\r
81 mem set 0x3fffc050 32 0xA55A0010 # RTCSR
\r
82 mem set 0x3fffe040 16 0x0000 # SDRAM_MODE_CS3
\r
83 # SRSR - SDRAM Setup?
\r
85 #SRSR - Not used - updated to include SDRAM setup
\r
86 # P7_6(WE0#), P7_8(RD#), P7_0(CS0#),
\r
87 #mem set 0xfcfe341c 16 0xff41 # PMC7
\r
88 #mem set 0xfcfe3A1c 16 0x0000 # PFCAE7
\r
89 #mem set 0xfcfe361c 16 0x0000 # PFCE7
\r
90 #mem set 0xfcfe351c 16 0x0000 # PFC7
\r
91 #mem set 0xfcfe721c 16 0xff41 # PIPC7
\r
92 #SRSR - Not used - updated to include SDRAM setup
\r