1 /******************************************************************************
3 * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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6 * of this software and associated documentation files (the "Software"), to deal
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9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
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15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
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31 ******************************************************************************/
32 /*****************************************************************************/
37 * MODIFICATION HISTORY:
39 * Ver Who Date Changes
40 * ----- ---- -------- ---------------------------------------------------
41 * 1.00a sdm 11/03/09 Initial release.
46 ******************************************************************************/
48 #ifndef SMC_H /* prevent circular inclusions */
49 #define SMC_H /* by using protection macros */
55 /***************************** Include Files *********************************/
57 #include "xparameters.h"
60 /***************** Macros (Inline Functions) Definitions *********************/
62 /**************************** Type Definitions *******************************/
64 /************************** Constant Definitions *****************************/
66 /* Memory controller configuration register offset */
67 #define XSMCPSS_MC_STATUS 0x000 /* Controller status reg, RO */
68 #define XSMCPSS_MC_INTERFACE_CONFIG 0x004 /* Interface config reg, RO */
69 #define XSMCPSS_MC_SET_CONFIG 0x008 /* Set configuration reg, WO */
70 #define XSMCPSS_MC_CLR_CONFIG 0x00C /* Clear config reg, WO */
71 #define XSMCPSS_MC_DIRECT_CMD 0x010 /* Direct command reg, WO */
72 #define XSMCPSS_MC_SET_CYCLES 0x014 /* Set cycles register, WO */
73 #define XSMCPSS_MC_SET_OPMODE 0x018 /* Set opmode register, WO */
74 #define XSMCPSS_MC_REFRESH_PERIOD_0 0x020 /* Refresh period_0 reg, RW */
75 #define XSMCPSS_MC_REFRESH_PERIOD_1 0x024 /* Refresh period_1 reg, RW */
77 /* Chip select configuration register offset */
78 #define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 config */
79 #define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 config */
80 #define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 config */
81 #define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 config */
82 #define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 config */
83 #define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 config */
84 #define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 config */
85 #define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 config */
87 /* User configuration register offset */
88 #define XSMCPSS_UC_STATUS_OFFSET 0x200 /* User status reg, RO */
89 #define XSMCPSS_UC_CONFIG_OFFSET 0x204 /* User config reg, WO */
91 /* Integration test register offset */
92 #define XSMCPSS_IT_OFFSET 0xE00
94 /* ID configuration register offset */
95 #define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0
96 #define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4
97 #define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8
98 #define XSMCPSS_ID_PERIP_3_OFFSET 0xFEC
99 #define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0
100 #define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4
101 #define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8
102 #define XSMCPSS_ID_PCELL_3_OFFSET 0xFFC
104 /************************** Variable Definitions *****************************/
106 /************************** Function Prototypes ******************************/
108 void XSmc_SramInit (void);
109 void XSmc_NorInit(void);
113 #endif /* __cplusplus */