1 /******************************************************************************
3 * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup devcfg_v3_1
39 * This file contains the hardware interface to the Device Config Interface.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- --- -------- ---------------------------------------------
46 * 1.00a hvm 02/07/11 First release
47 * 2.01a nm 08/01/12 Added defines for the PS Version bits,
48 * removed the FIFO Flush bits from the
49 * Miscellaneous Control Reg
50 * 2.03a nm 04/19/13 Fixed CR# 703728.
51 * Updated the register definitions as per the latest TRM
52 * version UG585 (v1.4) November 16, 2012.
53 * 2.04a kpc 10/07/13 Added function prototype.
54 * 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
57 ******************************************************************************/
58 #ifndef XDCFG_HW_H /* prevent circular inclusions */
59 #define XDCFG_HW_H /* by using protection macros */
65 /***************************** Include Files *********************************/
67 #include "xil_types.h"
70 /************************** Constant Definitions *****************************/
72 /** @name Register Map
73 * Offsets of registers from the start of the device
77 #define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
78 #define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
79 #define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
80 #define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
81 #define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
82 #define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
83 #define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
84 #define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
85 #define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
86 #define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
87 #define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
88 #define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
89 #define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
90 #define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
91 #define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
95 /** @name Control Register Bit definitions
99 #define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
102 #define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
105 #define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
106 #define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
107 #define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
108 #define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
109 * to FPGA every 4 PCAP
112 #define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
113 #define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
114 #define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
115 #define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
116 #define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
117 #define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
118 #define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
121 #define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
124 #define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
127 #define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
130 #define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
133 #define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
137 /** @name Lock register bit definitions
141 #define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
142 #define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
143 #define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
144 #define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
147 #define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
157 /** @name Config Register Bit definitions
160 #define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
163 #define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
166 #define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
169 #define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
172 #define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
175 #define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
182 /** @name Interrupt Status/Mask Register Bit definitions
185 #define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
188 #define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
191 #define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
192 #define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
195 #define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
198 #define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
199 * or Data or response
202 #define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
205 #define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
208 #define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
211 #define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
212 #define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
214 #define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
216 #define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
217 #define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
220 #define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
221 #define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
224 #define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
227 #define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
228 #define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
229 #define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
230 #define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
231 #define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
232 #define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
235 #define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
238 #define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
239 XDCFG_IXR_AXI_WERR_MASK | \
240 XDCFG_IXR_AXI_RTO_MASK | \
241 XDCFG_IXR_AXI_RERR_MASK | \
242 XDCFG_IXR_RX_FIFO_OV_MASK | \
243 XDCFG_IXR_DMA_CMD_ERR_MASK |\
244 XDCFG_IXR_DMA_Q_OV_MASK | \
245 XDCFG_IXR_P2D_LEN_ERR_MASK |\
246 XDCFG_IXR_PCFG_HMAC_ERR_MASK)
249 #define XDCFG_IXR_ALL_MASK 0x00F7F8EF
256 /** @name Status Register Bit definitions
259 #define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
262 #define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
265 #define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
269 #define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
270 #define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
272 #define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
275 #define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
278 #define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
279 #define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
282 #define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
285 #define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
288 #define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
291 #define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
294 #define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
298 #define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
301 #define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
308 /** @name DMA Source/Destination Transfer Length Register Bit definitions
311 #define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
317 /** @name Miscellaneous Control Register Bit definitions
320 #define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
321 #define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
322 #define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
325 /** @name FIFO Threshold Bit definitions
329 #define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
330 #define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
331 #define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
332 #define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
336 /* Miscellaneous constant values */
337 #define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
338 #define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
339 #define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
342 #define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
344 /**************************** Type Definitions *******************************/
346 /***************** Macros (Inline Functions) Definitions *********************/
348 /****************************************************************************/
351 * Read the given register.
353 * @param BaseAddr is the base address of the device
354 * @param RegOffset is the register offset to be read
356 * @return The 32-bit value of the register
358 * @note C-style signature:
359 * u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
361 *****************************************************************************/
362 #define XDcfg_ReadReg(BaseAddr, RegOffset) \
363 Xil_In32((BaseAddr) + (RegOffset))
365 /****************************************************************************/
368 * Write to the given register.
370 * @param BaseAddr is the base address of the device
371 * @param RegOffset is the register offset to be written
372 * @param Data is the 32-bit value to write to the register
376 * @note C-style signature:
377 * void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
379 *****************************************************************************/
380 #define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
381 Xil_Out32((BaseAddr) + (RegOffset), (Data))
383 /************************** Function Prototypes ******************************/
385 * Perform reset operation to the devcfg interface
387 void XDcfg_ResetHw(u32 BaseAddr);
388 /************************** Variable Definitions *****************************/
394 #endif /* end of protection macro */