git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h

   1 /******************************************************************************
   2 *
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   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
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   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
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  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
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  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /****************************************************************************/
  33 /**
  34 *
  35 * @file xdevcfg_hw.h
  36 *
  37 * This file contains the hardware interface to the Device Config Interface.
  38 *
  39 * <pre>
  40 * MODIFICATION HISTORY:
  41 *
  42 * Ver   Who Date     Changes
  43 * ----- --- -------- ---------------------------------------------
  44 * 1.00a hvm 02/07/11 First release
  45 * 2.01a nm  08/01/12 Added defines for the PS Version bits,
  46 *                    removed the FIFO Flush bits from the
  47 *                    Miscellaneous Control Reg
  48 * 2.03a nm  04/19/13 Fixed CR# 703728.
  49 *                    Updated the register definitions as per the latest TRM
  50 *                    version UG585 (v1.4) November 16, 2012.
  51 * 2.04a kpc     10/07/13 Added function prototype.
  52 * 3.00a kpc     25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
  53 * </pre>
  54 *
  55 ******************************************************************************/
  56 #ifndef XDCFG_HW_H              /* prevent circular inclusions */
  57 #define XDCFG_HW_H              /* by using protection macros */
  58
  59 #ifdef __cplusplus
  60 extern "C" {
  61 #endif
  62
  63 /***************************** Include Files *********************************/
  64
  65 #include "xil_types.h"
  66 #include "xil_io.h"
  67
  68 /************************** Constant Definitions *****************************/
  69
  70 /** @name Register Map
  71  * Offsets of registers from the start of the device
  72  * @{
  73  */
  74
  75 #define XDCFG_CTRL_OFFSET               0x00 /**< Control Register */
  76 #define XDCFG_LOCK_OFFSET               0x04 /**< Lock Register */
  77 #define XDCFG_CFG_OFFSET                0x08 /**< Configuration Register */
  78 #define XDCFG_INT_STS_OFFSET            0x0C /**< Interrupt Status Register */
  79 #define XDCFG_INT_MASK_OFFSET           0x10 /**< Interrupt Mask Register */
  80 #define XDCFG_STATUS_OFFSET             0x14 /**< Status Register */
  81 #define XDCFG_DMA_SRC_ADDR_OFFSET       0x18 /**< DMA Source Address Register */
  82 #define XDCFG_DMA_DEST_ADDR_OFFSET      0x1C /**< DMA Destination Address Reg */
  83 #define XDCFG_DMA_SRC_LEN_OFFSET        0x20 /**< DMA Source Transfer Length */
  84 #define XDCFG_DMA_DEST_LEN_OFFSET       0x24 /**< DMA Destination Transfer */
  85 #define XDCFG_ROM_SHADOW_OFFSET         0x28 /**< DMA ROM Shadow Register */
  86 #define XDCFG_MULTIBOOT_ADDR_OFFSET     0x2C /**< Multi BootAddress Pointer */
  87 #define XDCFG_SW_ID_OFFSET              0x30 /**< Software ID Register */
  88 #define XDCFG_UNLOCK_OFFSET             0x34 /**< Unlock Register */
  89 #define XDCFG_MCTRL_OFFSET              0x80 /**< Miscellaneous Control Reg */
  90
  91 /* @} */
  92
  93 /** @name Control Register Bit definitions
  94   * @{
  95  */
  96
  97 #define XDCFG_CTRL_FORCE_RST_MASK       0x80000000 /**< Force  into
  98                                                      * Secure Reset
  99                                                      */
 100 #define XDCFG_CTRL_PCFG_PROG_B_MASK     0x40000000 /**< Program signal to
 101                                                      *  Reset FPGA
 102                                                      */
 103 #define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
 104 #define XDCFG_CTRL_PCAP_PR_MASK         0x08000000 /**< Enable PCAP for PR */
 105 #define XDCFG_CTRL_PCAP_MODE_MASK       0x04000000 /**< Enable PCAP */
 106 #define XDCFG_CTRL_PCAP_RATE_EN_MASK    0x02000000 /**< Enable PCAP send data
 107                                                      *  to FPGA every 4 PCAP
 108                                                      *  cycles
 109                                                      */
 110 #define XDCFG_CTRL_MULTIBOOT_EN_MASK    0x01000000 /**< Multiboot Enable */
 111 #define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK  0x00800000 /**< JTAG Chain Disable */
 112 #define XDCFG_CTRL_USER_MODE_MASK       0x00008000 /**< User Mode Mask */
 113 #define XDCFG_CTRL_PCFG_AES_FUSE_MASK   0x00001000 /**< AES key source */
 114 #define XDCFG_CTRL_PCFG_AES_EN_MASK     0x00000E00 /**< AES Enable Mask */
 115 #define XDCFG_CTRL_SEU_EN_MASK          0x00000100 /**< SEU Enable Mask */
 116 #define XDCFG_CTRL_SEC_EN_MASK          0x00000080 /**< Secure/Non Secure
 117                                                      *  Status mask
 118                                                      */
 119 #define XDCFG_CTRL_SPNIDEN_MASK         0x00000040 /**< Secure Non Invasive
 120                                                      *  Debug Enable
 121                                                      */
 122 #define XDCFG_CTRL_SPIDEN_MASK          0x00000020 /**< Secure Invasive
 123                                                      *  Debug Enable
 124                                                      */
 125 #define XDCFG_CTRL_NIDEN_MASK           0x00000010 /**< Non-Invasive Debug
 126                                                      *  Enable
 127                                                      */
 128 #define XDCFG_CTRL_DBGEN_MASK           0x00000008 /**< Invasive Debug
 129                                                      *  Enable
 130                                                      */
 131 #define XDCFG_CTRL_DAP_EN_MASK          0x00000007 /**< DAP Enable Mask */
 132
 133 /* @} */
 134
 135 /** @name Lock register bit definitions
 136   * @{
 137  */
 138
 139 #define XDCFG_LOCK_AES_EFUSE_MASK       0x00000010 /**< Lock AES Efuse bit */
 140 #define XDCFG_LOCK_AES_EN_MASK          0x00000008 /**< Lock AES_EN update */
 141 #define XDCFG_LOCK_SEU_MASK             0x00000004 /**< Lock SEU_En update */
 142 #define XDCFG_LOCK_SEC_MASK             0x00000002 /**< Lock SEC_EN and
 143                                                      *  USER_MODE
 144                                                      */
 145 #define XDCFG_LOCK_DBG_MASK             0x00000001 /**< This bit locks
 146                                                      *  security config
 147                                                      *  including: DAP_En,
 148                                                      *  DBGEN,,
 149                                                      *  NIDEN, SPNIEN
 150                                                      */
 151 /*@}*/
 152
 153
 154
 155 /** @name Config Register Bit definitions
 156   * @{
 157  */
 158 #define XDCFG_CFG_RFIFO_TH_MASK         0x00000C00 /**< Read FIFO
 159                                                      *  Threshold Mask
 160                                                      */
 161 #define XDCFG_CFG_WFIFO_TH_MASK         0x00000300 /**< Write FIFO Threshold
 162                                                      *  Mask
 163                                                      */
 164 #define XDCFG_CFG_RCLK_EDGE_MASK        0x00000080 /**< Read data active
 165                                                      *  clock edge
 166                                                      */
 167 #define XDCFG_CFG_WCLK_EDGE_MASK        0x00000040 /**< Write data active
 168                                                      *  clock edge
 169                                                      */
 170 #define XDCFG_CFG_DISABLE_SRC_INC_MASK  0x00000020 /**< Disable Source address
 171                                                      *  increment mask
 172                                                      */
 173 #define XDCFG_CFG_DISABLE_DST_INC_MASK  0x00000010 /**< Disable Destination
 174                                                      *  address increment
 175                                                      *  mask
 176                                                      */
 177 /* @} */
 178
 179
 180 /** @name Interrupt Status/Mask Register Bit definitions
 181   * @{
 182  */
 183 #define XDCFG_IXR_PSS_GTS_USR_B_MASK    0x80000000 /**< Tri-state IO during
 184                                                      *  HIZ
 185                                                      */
 186 #define XDCFG_IXR_PSS_FST_CFG_B_MASK    0x40000000 /**< First configuration
 187                                                      *  done
 188                                                      */
 189 #define XDCFG_IXR_PSS_GPWRDWN_B_MASK    0x20000000 /**< Global power down */
 190 #define XDCFG_IXR_PSS_GTS_CFG_B_MASK    0x10000000 /**< Tri-state IO during
 191                                                      *  configuration
 192                                                      */
 193 #define XDCFG_IXR_PSS_CFG_RESET_B_MASK  0x08000000 /**< PL configuration
 194                                                      *  reset
 195                                                      */
 196 #define XDCFG_IXR_AXI_WTO_MASK          0x00800000 /**< AXI Write Address
 197                                                      *  or Data or response
 198                                                      *  timeout
 199                                                      */
 200 #define XDCFG_IXR_AXI_WERR_MASK         0x00400000 /**< AXI Write response
 201                                                      *  error
 202                                                      */
 203 #define XDCFG_IXR_AXI_RTO_MASK          0x00200000 /**< AXI Read Address or
 204                                                      *  response timeout
 205                                                      */
 206 #define XDCFG_IXR_AXI_RERR_MASK         0x00100000 /**< AXI Read response
 207                                                      *  error
 208                                                      */
 209 #define XDCFG_IXR_RX_FIFO_OV_MASK       0x00040000 /**< Rx FIFO Overflow */
 210 #define XDCFG_IXR_WR_FIFO_LVL_MASK      0x00020000 /**< Tx FIFO less than
 211                                                      *  threshold */
 212 #define XDCFG_IXR_RD_FIFO_LVL_MASK      0x00010000 /**< Rx FIFO greater than
 213                                                      *  threshold */
 214 #define XDCFG_IXR_DMA_CMD_ERR_MASK      0x00008000 /**< Illegal DMA command */
 215 #define XDCFG_IXR_DMA_Q_OV_MASK         0x00004000 /**< DMA command queue
 216                                                      *  overflow
 217                                                      */
 218 #define XDCFG_IXR_DMA_DONE_MASK         0x00002000 /**< DMA Command Done */
 219 #define XDCFG_IXR_D_P_DONE_MASK         0x00001000 /**< DMA and PCAP
 220                                                      *  transfers Done
 221                                                      */
 222 #define XDCFG_IXR_P2D_LEN_ERR_MASK      0x00000800 /**< PCAP to DMA transfer
 223                                                      *  length error
 224                                                      */
 225 #define XDCFG_IXR_PCFG_HMAC_ERR_MASK    0x00000040 /**< HMAC error mask */
 226 #define XDCFG_IXR_PCFG_SEU_ERR_MASK     0x00000020 /**< SEU Error mask */
 227 #define XDCFG_IXR_PCFG_POR_B_MASK       0x00000010 /**< FPGA POR mask */
 228 #define XDCFG_IXR_PCFG_CFG_RST_MASK     0x00000008 /**< FPGA Reset mask */
 229 #define XDCFG_IXR_PCFG_DONE_MASK        0x00000004 /**< Done Signal  Mask */
 230 #define XDCFG_IXR_PCFG_INIT_PE_MASK     0x00000002 /**< Detect Positive edge
 231                                                      *  of Init Signal
 232                                                      */
 233 #define XDCFG_IXR_PCFG_INIT_NE_MASK     0x00000001 /**< Detect Negative edge
 234                                                      *  of Init Signal
 235                                                      */
 236 #define XDCFG_IXR_ERROR_FLAGS_MASK              (XDCFG_IXR_AXI_WTO_MASK | \
 237                                                 XDCFG_IXR_AXI_WERR_MASK | \
 238                                                 XDCFG_IXR_AXI_RTO_MASK |  \
 239                                                 XDCFG_IXR_AXI_RERR_MASK | \
 240                                                 XDCFG_IXR_RX_FIFO_OV_MASK | \
 241                                                 XDCFG_IXR_DMA_CMD_ERR_MASK |\
 242                                                 XDCFG_IXR_DMA_Q_OV_MASK |   \
 243                                                 XDCFG_IXR_P2D_LEN_ERR_MASK |\
 244                                                 XDCFG_IXR_PCFG_HMAC_ERR_MASK)
 245
 246
 247 #define XDCFG_IXR_ALL_MASK                      0x00F7F8EF
 248
 249
 250
 251 /* @} */
 252
 253
 254 /** @name Status Register Bit definitions
 255   * @{
 256  */
 257 #define XDCFG_STATUS_DMA_CMD_Q_F_MASK   0x80000000 /**< DMA command
 258                                                      *  Queue full
 259                                                      */
 260 #define XDCFG_STATUS_DMA_CMD_Q_E_MASK   0x40000000 /**< DMA command
 261                                                      *  Queue empty
 262                                                      */
 263 #define XDCFG_STATUS_DMA_DONE_CNT_MASK  0x30000000 /**< Number of
 264                                                      *  completed DMA
 265                                                      *  transfers
 266                                                      */
 267 #define XDCFG_STATUS_RX_FIFO_LVL_MASK   0x01F000000 /**< Rx FIFO level */
 268 #define XDCFG_STATUS_TX_FIFO_LVL_MASK   0x0007F000  /**< Tx FIFO level */
 269
 270 #define XDCFG_STATUS_PSS_GTS_USR_B      0x00000800  /**< Tri-state IO
 271                                                       *  during HIZ
 272                                                       */
 273 #define XDCFG_STATUS_PSS_FST_CFG_B      0x00000400  /**< First PL config
 274                                                       *  done
 275                                                       */
 276 #define XDCFG_STATUS_PSS_GPWRDWN_B      0x00000200  /**< Global power down */
 277 #define XDCFG_STATUS_PSS_GTS_CFG_B      0x00000100  /**< Tri-state IO during
 278                                                       *  config
 279                                                       */
 280 #define XDCFG_STATUS_SECURE_RST_MASK    0x00000080  /**< Secure Reset
 281                                                       *  POR Status
 282                                                       */
 283 #define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK    0x00000040 /**< Illegal APB
 284                                                              *  access
 285                                                              */
 286 #define XDCFG_STATUS_PSS_CFG_RESET_B            0x00000020 /**< PL config
 287                                                              *  reset status
 288                                                              */
 289 #define XDCFG_STATUS_PCFG_INIT_MASK             0x00000010 /**< FPGA Init
 290                                                              *  Status
 291                                                              */
 292 #define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK       0x00000008
 293                                                            /**< BBRAM key
 294                                                              *  disable
 295                                                              */
 296 #define XDCFG_STATUS_EFUSE_SEC_EN_MASK          0x00000004 /**< Efuse Security
 297                                                              *  Enable Status
 298                                                              */
 299 #define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK        0x00000002 /**< EFuse JTAG
 300                                                              *  Disable
 301                                                              *  status
 302                                                              */
 303 /* @} */
 304
 305
 306 /** @name DMA Source/Destination Transfer Length Register Bit definitions
 307  * @{
 308  */
 309 #define XDCFG_DMA_LEN_MASK              0x7FFFFFF /**< Length Mask */
 310 /*@}*/
 311
 312
 313
 314
 315 /** @name Miscellaneous Control  Register Bit definitions
 316   * @{
 317  */
 318 #define XDCFG_MCTRL_PCAP_PS_VERSION_MASK  0xF0000000 /**< PS Version Mask */
 319 #define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28         /**< PS Version Shift */
 320 #define XDCFG_MCTRL_PCAP_LPBK_MASK        0x00000010 /**< PCAP loopback mask */
 321 /* @} */
 322
 323 /** @name FIFO Threshold Bit definitions
 324   * @{
 325  */
 326
 327 #define XDCFG_CFG_FIFO_QUARTER          0x0      /**< Quarter empty */
 328 #define XDCFG_CFG_FIFO_HALF             0x1      /**< Half empty */
 329 #define XDCFG_CFG_FIFO_3QUARTER         0x2      /**< 3/4 empty */
 330 #define XDCFG_CFG_FIFO_EMPTY            0x4      /**< Empty */
 331 /* @}*/
 332
 333
 334 /* Miscellaneous constant values */
 335 #define XDCFG_DMA_INVALID_ADDRESS       0xFFFFFFFF  /**< Invalid DMA address */
 336 #define XDCFG_UNLOCK_DATA               0x757BDF0D  /**< First APB access data*/
 337 #define XDCFG_BASE_ADDRESS              0xF8007000  /**< Device Config base
 338                                                       * address
 339                                                       */
 340 #define XDCFG_CONFIG_RESET_VALUE        0x508   /**< Config reg reset value */
 341
 342 /**************************** Type Definitions *******************************/
 343
 344 /***************** Macros (Inline Functions) Definitions *********************/
 345
 346 /****************************************************************************/
 347 /**
 348 *
 349 * Read the given register.
 350 *
 351 * @param        BaseAddr is the base address of the device
 352 * @param        RegOffset is the register offset to be read
 353 *
 354 * @return       The 32-bit value of the register
 355 *
 356 * @note         C-style signature:
 357 *               u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
 358 *
 359 *****************************************************************************/
 360 #define XDcfg_ReadReg(BaseAddr, RegOffset)              \
 361         Xil_In32((BaseAddr) + (RegOffset))
 362
 363 /****************************************************************************/
 364 /**
 365 *
 366 * Write to the given register.
 367 *
 368 * @param        BaseAddr is the base address of the device
 369 * @param        RegOffset is the register offset to be written
 370 * @param        Data is the 32-bit value to write to the register
 371 *
 372 * @return       None.
 373 *
 374 * @note         C-style signature:
 375 *               void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
 376 *
 377 *****************************************************************************/
 378 #define XDcfg_WriteReg(BaseAddr, RegOffset, Data)       \
 379         Xil_Out32((BaseAddr) + (RegOffset), (Data))
 380
 381 /************************** Function Prototypes ******************************/
 382 /*
 383  * Perform reset operation to the devcfg interface
 384  */
 385 void XDcfg_ResetHw(u32 BaseAddr);
 386 /************************** Variable Definitions *****************************/
 387
 388 #ifdef __cplusplus
 389 }
 390 #endif
 391
 392 #endif  /* end of protection macro */