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32 /****************************************************************************/
37 * The Xilinx Embedded Processor Block Ethernet driver.
39 * For a full description of XEMACPS features, please see the hardware spec.
40 * This driver supports the following features:
41 * - Memory mapped access to host interface registers
42 * - Statistics counter registers for RMON/MIB
43 * - API for interrupt driven frame transfers for hardware configured DMA
44 * - Virtual memory support
45 * - Unicast, broadcast, and multicast receive address filtering
46 * - Full and half duplex operation
47 * - Automatic PAD & FCS insertion and stripping
49 * - Support up to four 48bit addresses
50 * - Address checking for four specific 48bit addresses
51 * - VLAN frame support
52 * - Pause frame support
53 * - Large frame support up to 1536 bytes
56 * <b>Driver Description</b>
58 * The device driver enables higher layer software (e.g., an application) to
59 * communicate to the XEmacPs. The driver handles transmission and reception
60 * of Ethernet frames, as well as configuration and control. No pre or post
61 * processing of frame data is performed. The driver does not validate the
62 * contents of an incoming frame in addition to what has already occurred in
64 * A single device driver can support multiple devices even when those devices
65 * have significantly different configurations.
67 * <b>Initialization & Configuration</b>
69 * The XEmacPs_Config structure is used by the driver to configure itself.
70 * This configuration structure is typically created by the tool-chain based
71 * on hardware build properties.
73 * The driver instance can be initialized in
75 * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
76 * configuration structure provided by the caller. If running in a system
77 * with address translation, the provided virtual memory base address
78 * replaces the physical address present in the configuration structure.
80 * The device supports DMA only as current development plan. No FIFO mode is
81 * supported. The driver expects to start the DMA channels and expects that
82 * the user has set up the buffer descriptor lists.
84 * <b>Interrupts and Asynchronous Callbacks</b>
86 * The driver has no dependencies on the interrupt controller. When an
87 * interrupt occurs, the handler will perform a small amount of
88 * housekeeping work, determine the source of the interrupt, and call the
89 * appropriate callback function. All callbacks are registered by the user
92 * <b>Virtual Memory</b>
94 * All virtual to physical memory mappings must occur prior to accessing the
97 * For DMA transactions, user buffers supplied to the driver must be in terms
98 * of their physical address.
102 * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
103 * These BDs are typically chained together into a list the hardware follows
104 * when transferring data in and out of the packet buffers. Each BD describes
105 * a memory region containing either a full or partial Ethernet packet.
107 * Interrupt coalescing is not suppoted from this built-in DMA engine.
109 * This API requires the user to understand how the DMA operates. The
110 * following paragraphs provide some explanation, but the user is encouraged
111 * to read documentation in xemacps_bdring.h as well as study example code
112 * that accompanies this driver.
114 * The API is designed to get BDs to and from the DMA engine in the most
115 * efficient means possible. The first step is to establish a memory region
116 * to contain all BDs for a specific channel. This is done with
117 * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
118 * follow as BDs are processed. The ring will consist of a user defined number
119 * of BDs which will all be partially initialized. For example on the transmit
120 * channel, the driver will initialize all BDs' so that they are configured
121 * for transmit. The more fields that can be permanently setup at
122 * initialization, then the fewer accesses will be needed to each BD while
123 * the DMA engine is in operation resulting in better throughput and CPU
124 * utilization. The best case initialization would require the user to set
125 * only a frame buffer address and length prior to submitting the BD to the
128 * BDs move through the engine with the help of functions
129 * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
130 * and XEmacPs_BdRingFree().
131 * All these functions handle BDs that are in place. That is, there are no
132 * copies of BDs kept anywhere and any BD the user interacts with is an actual
133 * BD from the same ring hardware accesses.
135 * BDs in the ring go through a series of states as follows:
136 * 1. Idle. The driver controls BDs in this state.
137 * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
138 * reserve BD(s). Once allocated, the user may setup the BD(s) with
139 * frame buffer address, length, and other attributes. The user controls
141 * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
142 * in this state are either waiting to be processed by hardware, are in
143 * process, or have been processed. The DMA engine controls BDs in this
145 * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
146 * user. Once retrieved, the user can examine each BD for the outcome of
147 * the DMA transfer. The user controls BDs in this state. After examining
148 * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
151 * Each of the four BD accessor functions operate on a set of BDs. A set is
152 * defined as a segment of the BD ring consisting of one or more BDs. The user
153 * views the set as a pointer to the first BD along with the number of BDs for
154 * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
155 * user must exercise extreme caution when changing BDs in a set as there is
156 * nothing to prevent doing a mBdNext past the end of the set and modifying a
159 * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
160 * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
161 * tandem. The same BD set retrieved with BdRingAlloc should be the same one
162 * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
165 * <b>Alignment & Data Cache Restrictions</b>
167 * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
168 * aligned. Please reference xemacps_bd.h for cache related macros.
172 * - If frame buffers exist in cached memory, then they must be flushed
173 * prior to committing them to hardware.
177 * - If frame buffers exist in cached memory, then the cache must be
178 * invalidated for the memory region containing the frame prior to data
181 * Both cache invalidate/flush are taken care of in driver code.
183 * <b>Buffer Copying</b>
185 * The driver is designed for a zero-copy buffer scheme. That is, the driver
186 * will not copy buffers. This avoids potential throughput bottlenecks within
187 * the driver. If byte copying is required, then the transfer will take longer
190 * <b>Checksum Offloading</b>
192 * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
193 * and UDP checksum offloading in both receive and transmit directions.
195 * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
196 * complement of the 1s complement sum of all 16-bit words in the header.
197 * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
198 * 1s complement of the 1s complement sum of all 16-bit words in the header,
199 * the data and a conceptual pseudo header.
201 * To calculate these checksums in software requires each byte of the packet
202 * to be read. For TCP and UDP this can use a large amount of processing power.
203 * Offloading the checksum calculation to hardware can result in significant
204 * performance improvements.
206 * The transmit checksum offload is only available to use DMA in packet buffer
207 * mode. This is because the complete frame to be transmitted must be read
208 * into the packet buffer memory before the checksum can be calculated and
209 * written to the header at the beginning of the frame.
211 * For IP, TCP or UDP receive checksum offload to be useful, the operating
212 * system containing the protocol stack must be aware that this offload is
213 * available so that it can make use of the fact that the hardware has verified
216 * When receive checksum offloading is enabled in the hardware, the IP header
217 * checksum is checked, where the packet meets the following criteria:
219 * 1. If present, the VLAN header must be four octets long and the CFI bit
221 * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
224 * 4. IP header is of a valid length.
225 * 5. Good IP header checksum.
226 * 6. No IP fragmentation.
227 * 7. TCP or UDP packet.
229 * When an IP, TCP or UDP frame is received, the receive buffer descriptor
230 * gives an indication if the hardware was able to verify the checksums.
231 * There is also an indication if the frame had SNAP encapsulation. These
232 * indication bits will replace the type ID match indication bits when the
233 * receive checksum offload is enabled.
235 * If any of the checksums are verified incorrect by the hardware, the packet
236 * is discarded and the appropriate statistics counter incremented.
238 * <b>PHY Interfaces</b>
240 * RGMII 1.3 is the only interface supported.
244 * Asserts are used within all Xilinx drivers to enforce constraints on
245 * parameters. Asserts can be turned off on a system-wide basis by defining,
246 * at compile time, the NDEBUG identifier. By default, asserts are turned on
247 * and it is recommended that users leave asserts on during development. For
248 * deployment use -DNDEBUG compiler switch to remove assert code.
252 * Xilinx drivers are typically composed of two parts, one is the driver
253 * and the other is the adapter. The driver is independent of OS and processor
254 * and is intended to be highly portable. The adapter is OS-specific and
255 * facilitates communication between the driver and an OS.
256 * This driver is intended to be RTOS and processor independent. Any needs for
257 * dynamic memory management, threads or thread mutual exclusion, or cache
258 * control must be satisfied bythe layer above this driver.
261 * MODIFICATION HISTORY:
263 * Ver Who Date Changes
264 * ----- ---- -------- -------------------------------------------------------
265 * 1.00a wsy 01/10/10 First release
266 * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
267 * xemacps_bdring.c is modified. Earlier it was checking for
268 * "BdLimit"(passed argument) number of BDs for finding out
269 * which BDs are successfully processed. Now one more check
270 * is added. It looks for BDs till the current BD pointer
271 * reaches HwTail. By doing this processing time is saved.
272 * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
273 * xemacps_bdring.c is modified. Now start of packet is
274 * searched for returning the number of BDs processed.
275 * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
276 * registers. Added a new API to set the bust length.
277 * Added some new hash-defines.
278 * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
279 * Rx errors. Under heavy Rx traffic, there will be a large
280 * number of errors related to receive buffer not available.
281 * Because of a HW bug (SI #692601), under such heavy errors,
282 * the Rx data path can become unresponsive. To reduce the
283 * probabilities for hitting this HW bug, the SW writes to
284 * bit 18 to flush a packet from Rx DPRAM immediately. The
285 * changes for it are done in the function
286 * XEmacPs_IntrHandler.
287 * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
288 * removed. It is expected that all BDs are allocated in
289 * from uncached area.
290 * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
291 * to 0x1fff. This fixes the CR#744902.
292 * Made changes in example file xemacps_example.h to fix compilation
293 * issues with iarcc compiler.
294 * 2.0 adk 10/12/13 Updated as per the New Tcl API's
297 ****************************************************************************/
299 #ifndef XEMACPS_H /* prevent circular inclusions */
300 #define XEMACPS_H /* by using protection macros */
306 /***************************** Include Files ********************************/
308 #include "xil_types.h"
309 #include "xil_assert.h"
311 #include "xemacps_hw.h"
312 #include "xemacps_bd.h"
313 #include "xemacps_bdring.h"
315 /************************** Constant Definitions ****************************/
320 #define XEMACPS_DEVICE_NAME "xemacps"
321 #define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
324 /** @name Configuration options
326 * Device configuration options. See the XEmacPs_SetOptions(),
327 * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
330 * The default state of the options are noted and are what the device and
331 * driver will be set to after calling XEmacPs_Reset() or
332 * XEmacPs_Initialize().
337 #define XEMACPS_PROMISC_OPTION 0x00000001
338 /**< Accept all incoming packets.
339 * This option defaults to disabled (cleared) */
341 #define XEMACPS_FRAME1536_OPTION 0x00000002
342 /**< Frame larger than 1516 support for Tx & Rx.
343 * This option defaults to disabled (cleared) */
345 #define XEMACPS_VLAN_OPTION 0x00000004
346 /**< VLAN Rx & Tx frame support.
347 * This option defaults to disabled (cleared) */
349 #define XEMACPS_FLOW_CONTROL_OPTION 0x00000010
350 /**< Enable recognition of flow control frames on Rx
351 * This option defaults to enabled (set) */
353 #define XEMACPS_FCS_STRIP_OPTION 0x00000020
354 /**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
356 * This option defaults to enabled (set) */
358 #define XEMACPS_FCS_INSERT_OPTION 0x00000040
359 /**< Generate FCS field and add PAD automatically for outgoing frames.
360 * This option defaults to disabled (cleared) */
362 #define XEMACPS_LENTYPE_ERR_OPTION 0x00000080
363 /**< Enable Length/Type error checking for incoming frames. When this option is
364 * set, the MAC will filter frames that have a mismatched type/length field
365 * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
366 * types of frames are encountered. When this option is cleared, the MAC will
367 * allow these types of frames to be received.
369 * This option defaults to disabled (cleared) */
371 #define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100
372 /**< Enable the transmitter.
373 * This option defaults to enabled (set) */
375 #define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200
376 /**< Enable the receiver
377 * This option defaults to enabled (set) */
379 #define XEMACPS_BROADCAST_OPTION 0x00000400
380 /**< Allow reception of the broadcast address
381 * This option defaults to enabled (set) */
383 #define XEMACPS_MULTICAST_OPTION 0x00000800
384 /**< Allows reception of multicast addresses programmed into hash
385 * This option defaults to disabled (clear) */
387 #define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000
388 /**< Enable the RX checksum offload
389 * This option defaults to enabled (set) */
391 #define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000
392 /**< Enable the TX checksum offload
393 * This option defaults to enabled (set) */
396 #define XEMACPS_DEFAULT_OPTIONS \
397 (XEMACPS_FLOW_CONTROL_OPTION | \
398 XEMACPS_FCS_INSERT_OPTION | \
399 XEMACPS_FCS_STRIP_OPTION | \
400 XEMACPS_BROADCAST_OPTION | \
401 XEMACPS_LENTYPE_ERR_OPTION | \
402 XEMACPS_TRANSMITTER_ENABLE_OPTION | \
403 XEMACPS_RECEIVER_ENABLE_OPTION | \
404 XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
405 XEMACPS_TX_CHKSUM_ENABLE_OPTION)
407 /**< Default options set when device is initialized or reset */
410 /** @name Callback identifiers
412 * These constants are used as parameters to XEmacPs_SetHandler()
415 #define XEMACPS_HANDLER_DMASEND 1
416 #define XEMACPS_HANDLER_DMARECV 2
417 #define XEMACPS_HANDLER_ERROR 3
420 /* Constants to determine the configuration of the hardware device. They are
421 * used to allow the driver to verify it can operate with the hardware.
423 #define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
425 /* The next few constants help upper layers determine the size of memory
426 * pools used for Ethernet buffers and descriptor lists.
428 #define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */
430 #define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */
431 #define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */
432 #define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
433 #define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
434 #define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
436 #define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
437 XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
439 /* DMACR Bust length hash defines */
441 #define XEMACPS_SINGLE_BURST 1
442 #define XEMACPS_4BYTE_BURST 4
443 #define XEMACPS_8BYTE_BURST 8
444 #define XEMACPS_16BYTE_BURST 16
447 /**************************** Type Definitions ******************************/
448 /** @name Typedefs for callback functions
450 * These callbacks are invoked in interrupt context.
454 * Callback invoked when frame(s) have been sent or received in interrupt
455 * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
457 * @param CallBackRef is user data assigned when the callback was set.
460 * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
461 * further information on their meaning.
464 typedef void (*XEmacPs_Handler) (void *CallBackRef);
467 * Callback when an asynchronous error occurs. To set this callback, invoke
468 * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
471 * @param CallBackRef is user data assigned when the callback was set.
472 * @param Direction defines either receive or transmit error(s) has occurred.
473 * @param ErrorWord definition varies with Direction
476 typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
482 * This typedef contains configuration information for a device.
485 u16 DeviceId; /**< Unique ID of device */
486 u32 BaseAddress;/**< Physical base address of IPIF registers */
491 * The XEmacPs driver instance data. The user is required to allocate a
492 * structure of this type for every XEmacPs device in the system. A pointer
493 * to a structure of this type is then passed to the driver API functions.
495 typedef struct XEmacPs {
496 XEmacPs_Config Config; /* Hardware configuration */
497 u32 IsStarted; /* Device is currently started */
498 u32 IsReady; /* Device is initialized and ready */
499 u32 Options; /* Current options word */
501 XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
502 XEmacPs_BdRing RxBdRing; /* Receive BD ring */
504 XEmacPs_Handler SendHandler;
505 XEmacPs_Handler RecvHandler;
509 XEmacPs_ErrHandler ErrorHandler;
515 /***************** Macros (Inline Functions) Definitions ********************/
517 /****************************************************************************/
519 * Retrieve the Tx ring object. This object can be used in the various Ring
522 * @param InstancePtr is the DMA channel to operate on.
524 * @return TxBdRing attribute
528 * XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
530 *****************************************************************************/
531 #define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
533 /****************************************************************************/
535 * Retrieve the Rx ring object. This object can be used in the various Ring
538 * @param InstancePtr is the DMA channel to operate on.
540 * @return RxBdRing attribute
544 * XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
546 *****************************************************************************/
547 #define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
549 /****************************************************************************/
552 * Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
553 * each bit set to 1 in <i>Mask</i>, will be enabled.
555 * @param InstancePtr is a pointer to the instance to be worked on.
556 * @param Mask contains a bit mask of interrupts to enable. The mask can
557 * be formed using a set of bitwise or'd values.
560 * The state of the transmitter and receiver are not modified by this function.
562 * void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
564 *****************************************************************************/
565 #define XEmacPs_IntEnable(InstancePtr, Mask) \
566 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
567 XEMACPS_IER_OFFSET, \
568 (Mask & XEMACPS_IXR_ALL_MASK));
570 /****************************************************************************/
573 * Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
574 * each bit set to 1 in <i>Mask</i>, will be enabled.
576 * @param InstancePtr is a pointer to the instance to be worked on.
577 * @param Mask contains a bit mask of interrupts to disable. The mask can
578 * be formed using a set of bitwise or'd values.
581 * The state of the transmitter and receiver are not modified by this function.
583 * void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
585 *****************************************************************************/
586 #define XEmacPs_IntDisable(InstancePtr, Mask) \
587 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
588 XEMACPS_IDR_OFFSET, \
589 (Mask & XEMACPS_IXR_ALL_MASK));
591 /****************************************************************************/
594 * This macro triggers trasmit circuit to send data currently in TX buffer(s).
596 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
602 * Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
604 *****************************************************************************/
605 #define XEmacPs_Transmit(InstancePtr) \
606 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \
607 XEMACPS_NWCTRL_OFFSET, \
608 (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \
609 XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
611 /****************************************************************************/
614 * This macro determines if the device is configured with checksum offloading
615 * on the receive channel
617 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
621 * Boolean TRUE if the device is configured with checksum offloading, or
626 * Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
628 *****************************************************************************/
629 #define XEmacPs_IsRxCsum(InstancePtr) \
630 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
631 XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \
634 /****************************************************************************/
637 * This macro determines if the device is configured with checksum offloading
638 * on the transmit channel
640 * @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
644 * Boolean TRUE if the device is configured with checksum offloading, or
649 * Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
651 *****************************************************************************/
652 #define XEmacPs_IsTxCsum(InstancePtr) \
653 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
654 XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \
657 /************************** Function Prototypes *****************************/
660 * Initialization functions in xemacps.c
662 int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
663 u32 EffectiveAddress);
664 void XEmacPs_Start(XEmacPs *InstancePtr);
665 void XEmacPs_Stop(XEmacPs *InstancePtr);
666 void XEmacPs_Reset(XEmacPs *InstancePtr);
669 * Lookup configuration in xemacps_sinit.c
671 XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
674 * Interrupt-related functions in xemacps_intr.c
675 * DMA only and FIFO is not supported. This DMA does not support coalescing.
677 int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
678 void *FuncPtr, void *CallBackRef);
679 void XEmacPs_IntrHandler(void *InstancePtr);
682 * MAC configuration/control functions in XEmacPs_control.c
684 int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
685 int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
686 u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
688 int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
689 void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
691 int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
692 void XEmacPs_ClearHash(XEmacPs *InstancePtr);
693 void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
695 void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
696 XEmacPs_MdcDiv Divisor);
697 void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
698 u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
699 int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
700 u32 RegisterNum, u16 *PhyDataPtr);
701 int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
702 u32 RegisterNum, u16 PhyData);
703 int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
705 int XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
706 void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength);
712 #endif /* end of protection macro */