1 /******************************************************************************
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31 ******************************************************************************/
32 /*****************************************************************************/
37 * The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
40 * The GPIO Controller supports the following features:
42 * - Masked writes (There are no masked reads)
44 * - Configurable Interrupts (Level/Edge)
46 * This driver is intended to be RTOS and processor independent. Any needs for
47 * dynamic memory management, threads or thread mutual exclusion, virtual
48 * memory, or cache control must be satisfied by the layer above this driver.
50 * This driver supports all the features listed above, if applicable.
52 * <b>Driver Description</b>
54 * The device driver enables higher layer software (e.g., an application) to
55 * communicate to the GPIO.
59 * The driver provides interrupt management functions and an interrupt handler.
60 * Users of this driver need to provide callback functions. An interrupt handler
61 * example is available with the driver.
65 * This driver is not thread safe. Any needs for threads or thread mutual
66 * exclusion must be satisfied by the layer above this driver.
70 * Asserts are used within all Xilinx drivers to enforce constraints on argument
71 * values. Asserts can be turned off on a system-wide basis by defining, at
72 * compile time, the NDEBUG identifier. By default, asserts are turned on and it
73 * is recommended that users leave asserts on during development.
75 * <b>Building the driver</b>
77 * The XGpioPs driver is composed of several source files. This allows the user
78 * to build and link only those parts of the driver that are necessary.
82 * MODIFICATION HISTORY:
84 * Ver Who Date Changes
85 * ----- ---- -------- -----------------------------------------------
86 * 1.00a sv 01/15/10 First Release
87 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
88 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
89 * relevant to Zynq device.The interrupts are disabled
90 * for output pins on all banks during initialization.
91 * 1.02a hk 08/22/13 Added low level reset API
92 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
96 ******************************************************************************/
97 #ifndef XGPIOPS_H /* prevent circular inclusions */
98 #define XGPIOPS_H /* by using protection macros */
104 /***************************** Include Files *********************************/
107 #include "xgpiops_hw.h"
109 /************************** Constant Definitions *****************************/
111 /** @name Interrupt types
113 * The following constants define the interrupt types that can be set for each
116 #define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */
117 #define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */
118 #define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */
119 #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */
120 #define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */
123 #define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */
124 #define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */
125 #define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */
126 #define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */
128 #define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */
129 #define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */
131 #define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device
138 /**************************** Type Definitions *******************************/
140 /****************************************************************************/
142 * This handler data type allows the user to define a callback function to
143 * handle the interrupts for the GPIO device. The application using this
144 * driver is expected to define a handler of this type, to support interrupt
145 * driven mode. The handler executes in an interrupt context such that minimal
146 * processing should be performed.
148 * @param CallBackRef is a callback reference passed in by the upper layer
149 * when setting the callback functions for a GPIO bank. It is
150 * passed back to the upper layer when the callback is invoked. Its
151 * type is not important to the driver component, so it is a void
153 * @param Bank is the bank for which the interrupt status has changed.
154 * @param Status is the Interrupt status of the GPIO bank.
156 *****************************************************************************/
157 typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status);
160 * This typedef contains configuration information for a device.
163 u16 DeviceId; /**< Unique ID of device */
164 u32 BaseAddr; /**< Register base address */
168 * The XGpioPs driver instance data. The user is required to allocate a
169 * variable of this type for the GPIO device in the system. A pointer
170 * to a variable of this type is then passed to the driver API functions.
173 XGpioPs_Config GpioConfig; /**< Device configuration */
174 u32 IsReady; /**< Device is initialized and ready */
175 XGpioPs_Handler Handler; /**< Status handlers for all banks */
176 void *CallBackRef; /**< Callback ref for bank handlers */
179 /***************** Macros (Inline Functions) Definitions *********************/
181 /************************** Function Prototypes ******************************/
184 * Functions in xgpiops.c
186 int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
190 * Bank APIs in xgpiops.c
192 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
193 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
194 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
195 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
196 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable);
197 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
198 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
201 * Pin APIs in xgpiops.c
203 int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin);
204 void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data);
205 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction);
206 int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin);
207 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable);
208 int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin);
211 * Diagnostic functions in xgpiops_selftest.c
213 int XGpioPs_SelfTest(XGpioPs *InstancePtr);
216 * Functions in xgpiops_intr.c
219 * Bank APIs in xgpiops_intr.c
221 void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
222 void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
223 u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
224 u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
225 void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
226 void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
227 u32 IntrPolarity, u32 IntrOnAny);
228 void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
229 u32 *IntrPolarity, u32 *IntrOnAny);
230 void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
231 XGpioPs_Handler FuncPtr);
232 void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
235 * Pin APIs in xgpiops_intr.c
237 void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType);
238 u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin);
240 void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin);
241 void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin);
242 int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin);
243 int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin);
244 void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin);
247 * Functions in xgpiops_sinit.c
249 XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
255 #endif /* end of protection macro */