1 /* Definition for CPU ID */
\r
2 #define XPAR_CPU_ID 0
\r
4 /* Definitions for peripheral PS7_CORTEXA9_0 */
\r
5 #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
\r
8 /******************************************************************/
\r
10 /* Canonical definitions for peripheral PS7_CORTEXA9_0 */
\r
11 #define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
\r
14 /******************************************************************/
\r
16 #include "xparameters_ps.h"
\r
18 #define STDIN_BASEADDRESS 0xE0001000
\r
19 #define STDOUT_BASEADDRESS 0xE0001000
\r
21 /******************************************************************/
\r
23 /* Definitions for driver CANPS */
\r
24 #define XPAR_XCANPS_NUM_INSTANCES 1
\r
26 /* Definitions for peripheral PS7_CAN_0 */
\r
27 #define XPAR_PS7_CAN_0_DEVICE_ID 0
\r
28 #define XPAR_PS7_CAN_0_BASEADDR 0xE0008000
\r
29 #define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF
\r
30 #define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523
\r
33 /******************************************************************/
\r
35 /* Canonical definitions for peripheral PS7_CAN_0 */
\r
36 #define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID
\r
37 #define XPAR_XCANPS_0_BASEADDR 0xE0008000
\r
38 #define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF
\r
39 #define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523
\r
42 /******************************************************************/
\r
45 /* Definitions for peripheral PS7_DDR_0 */
\r
46 #define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
\r
47 #define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
\r
50 /******************************************************************/
\r
52 /* Definitions for driver DEVCFG */
\r
53 #define XPAR_XDCFG_NUM_INSTANCES 1
\r
55 /* Definitions for peripheral PS7_DEV_CFG_0 */
\r
56 #define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
\r
57 #define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
\r
58 #define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
\r
61 /******************************************************************/
\r
63 /* Canonical definitions for peripheral PS7_DEV_CFG_0 */
\r
64 #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
\r
65 #define XPAR_XDCFG_0_BASEADDR 0xF8007000
\r
66 #define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
\r
69 /******************************************************************/
\r
71 /* Definitions for driver DMAPS */
\r
72 #define XPAR_XDMAPS_NUM_INSTANCES 2
\r
74 /* Definitions for peripheral PS7_DMA_NS */
\r
75 #define XPAR_PS7_DMA_NS_DEVICE_ID 0
\r
76 #define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
\r
77 #define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
\r
80 /* Definitions for peripheral PS7_DMA_S */
\r
81 #define XPAR_PS7_DMA_S_DEVICE_ID 1
\r
82 #define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
\r
83 #define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
\r
86 /******************************************************************/
\r
88 /* Canonical definitions for peripheral PS7_DMA_NS */
\r
89 #define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
\r
90 #define XPAR_XDMAPS_0_BASEADDR 0xF8004000
\r
91 #define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
\r
93 /* Canonical definitions for peripheral PS7_DMA_S */
\r
94 #define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
\r
95 #define XPAR_XDMAPS_1_BASEADDR 0xF8003000
\r
96 #define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
\r
99 /******************************************************************/
\r
101 /* Definitions for driver EMACPS */
\r
102 #define XPAR_XEMACPS_NUM_INSTANCES 1
\r
104 /* Definitions for peripheral PS7_ETHERNET_0 */
\r
105 #define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
\r
106 #define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
\r
107 #define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
\r
108 #define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000
\r
109 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
\r
110 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
\r
111 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
\r
112 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
\r
113 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
\r
114 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
\r
117 /******************************************************************/
\r
119 /* Canonical definitions for peripheral PS7_ETHERNET_0 */
\r
120 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
\r
121 #define XPAR_XEMACPS_0_BASEADDR 0xE000B000
\r
122 #define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
\r
123 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000
\r
124 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
\r
125 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
\r
126 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
\r
127 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
\r
128 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
\r
129 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
\r
132 /******************************************************************/
\r
135 /* Definitions for peripheral PS7_AFI_0 */
\r
136 #define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
\r
137 #define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
\r
140 /* Definitions for peripheral PS7_AFI_1 */
\r
141 #define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
\r
142 #define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
\r
145 /* Definitions for peripheral PS7_AFI_2 */
\r
146 #define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
\r
147 #define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
\r
150 /* Definitions for peripheral PS7_AFI_3 */
\r
151 #define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
\r
152 #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
\r
155 /* Definitions for peripheral PS7_DDRC_0 */
\r
156 #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
\r
157 #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
\r
160 /* Definitions for peripheral PS7_GLOBALTIMER_0 */
\r
161 #define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
\r
162 #define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
\r
165 /* Definitions for peripheral PS7_GPV_0 */
\r
166 #define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
\r
167 #define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
\r
170 /* Definitions for peripheral PS7_INTC_DIST_0 */
\r
171 #define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
\r
172 #define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
\r
175 /* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
\r
176 #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
\r
177 #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
\r
180 /* Definitions for peripheral PS7_L2CACHEC_0 */
\r
181 #define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
\r
182 #define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
\r
185 /* Definitions for peripheral PS7_OCMC_0 */
\r
186 #define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
\r
187 #define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
\r
190 /* Definitions for peripheral PS7_PL310_0 */
\r
191 #define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
\r
192 #define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
\r
195 /* Definitions for peripheral PS7_PMU_0 */
\r
196 #define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
\r
197 #define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
\r
198 #define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
\r
199 #define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
\r
202 /* Definitions for peripheral PS7_QSPI_LINEAR_0 */
\r
203 #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
\r
204 #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
\r
207 /* Definitions for peripheral PS7_RAM_0 */
\r
208 #define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
\r
209 #define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
\r
212 /* Definitions for peripheral PS7_RAM_1 */
\r
213 #define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
\r
214 #define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
\r
217 /* Definitions for peripheral PS7_SCUC_0 */
\r
218 #define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
\r
219 #define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
\r
222 /* Definitions for peripheral PS7_SLCR_0 */
\r
223 #define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
\r
224 #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
\r
227 /******************************************************************/
\r
229 /* Definitions for driver GPIOPS */
\r
230 #define XPAR_XGPIOPS_NUM_INSTANCES 1
\r
232 /* Definitions for peripheral PS7_GPIO_0 */
\r
233 #define XPAR_PS7_GPIO_0_DEVICE_ID 0
\r
234 #define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
\r
235 #define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
\r
238 /******************************************************************/
\r
240 /* Canonical definitions for peripheral PS7_GPIO_0 */
\r
241 #define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
\r
242 #define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
\r
243 #define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
\r
246 /******************************************************************/
\r
248 /* Definitions for driver IICPS */
\r
249 #define XPAR_XIICPS_NUM_INSTANCES 1
\r
251 /* Definitions for peripheral PS7_I2C_0 */
\r
252 #define XPAR_PS7_I2C_0_DEVICE_ID 0
\r
253 #define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
\r
254 #define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
\r
255 #define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
\r
258 /******************************************************************/
\r
260 /* Canonical definitions for peripheral PS7_I2C_0 */
\r
261 #define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
\r
262 #define XPAR_XIICPS_0_BASEADDR 0xE0004000
\r
263 #define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
\r
264 #define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
\r
267 /******************************************************************/
\r
269 /* Definitions for driver QSPIPS */
\r
270 #define XPAR_XQSPIPS_NUM_INSTANCES 1
\r
272 /* Definitions for peripheral PS7_QSPI_0 */
\r
273 #define XPAR_PS7_QSPI_0_DEVICE_ID 0
\r
274 #define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
\r
275 #define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
\r
276 #define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
\r
277 #define XPAR_PS7_QSPI_0_QSPI_MODE 0
\r
280 /******************************************************************/
\r
282 /* Canonical definitions for peripheral PS7_QSPI_0 */
\r
283 #define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
\r
284 #define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
\r
285 #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
\r
286 #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
\r
287 #define XPAR_XQSPIPS_0_QSPI_MODE 0
\r
290 /******************************************************************/
\r
292 /* Definitions for driver SCUGIC */
\r
293 #define XPAR_XSCUGIC_NUM_INSTANCES 1
\r
295 /* Definitions for peripheral PS7_SCUGIC_0 */
\r
296 #define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
\r
297 #define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
\r
298 #define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
\r
299 #define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
\r
302 /******************************************************************/
\r
304 /* Canonical definitions for peripheral PS7_SCUGIC_0 */
\r
305 #define XPAR_SCUGIC_0_DEVICE_ID 0
\r
306 #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
\r
307 #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
\r
308 #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
\r
311 /******************************************************************/
\r
313 /* Definitions for driver SCUTIMER */
\r
314 #define XPAR_XSCUTIMER_NUM_INSTANCES 1
\r
316 /* Definitions for peripheral PS7_SCUTIMER_0 */
\r
317 #define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
\r
318 #define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
\r
319 #define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
\r
322 /******************************************************************/
\r
324 /* Canonical definitions for peripheral PS7_SCUTIMER_0 */
\r
325 #define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
\r
326 #define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
\r
327 #define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
\r
330 /******************************************************************/
\r
332 /* Definitions for driver SCUWDT */
\r
333 #define XPAR_XSCUWDT_NUM_INSTANCES 1
\r
335 /* Definitions for peripheral PS7_SCUWDT_0 */
\r
336 #define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
\r
337 #define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
\r
338 #define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
\r
341 /******************************************************************/
\r
343 /* Canonical definitions for peripheral PS7_SCUWDT_0 */
\r
344 #define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
\r
345 #define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
\r
346 #define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
\r
349 /******************************************************************/
\r
351 /* Definitions for driver SDPS */
\r
352 #define XPAR_XSDPS_NUM_INSTANCES 1
\r
354 /* Definitions for peripheral PS7_SD_0 */
\r
355 #define XPAR_PS7_SD_0_DEVICE_ID 0
\r
356 #define XPAR_PS7_SD_0_BASEADDR 0xE0100000
\r
357 #define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
\r
358 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
\r
359 #define XPAR_PS7_SD_0_HAS_CD 1
\r
360 #define XPAR_PS7_SD_0_HAS_WP 1
\r
363 /******************************************************************/
\r
365 /* Canonical definitions for peripheral PS7_SD_0 */
\r
366 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
\r
367 #define XPAR_XSDPS_0_BASEADDR 0xE0100000
\r
368 #define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
\r
369 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
\r
370 #define XPAR_XSDPS_0_HAS_CD 1
\r
371 #define XPAR_XSDPS_0_HAS_WP 1
\r
374 /******************************************************************/
\r
376 /* Definitions for driver TTCPS */
\r
377 #define XPAR_XTTCPS_NUM_INSTANCES 3
\r
379 /* Definitions for peripheral PS7_TTC_0 */
\r
380 #define XPAR_PS7_TTC_0_DEVICE_ID 0
\r
381 #define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
\r
382 #define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
\r
383 #define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
\r
384 #define XPAR_PS7_TTC_1_DEVICE_ID 1
\r
385 #define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
\r
386 #define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
\r
387 #define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
\r
388 #define XPAR_PS7_TTC_2_DEVICE_ID 2
\r
389 #define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
\r
390 #define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
\r
391 #define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
\r
394 /******************************************************************/
\r
396 /* Canonical definitions for peripheral PS7_TTC_0 */
\r
397 #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
\r
398 #define XPAR_XTTCPS_0_BASEADDR 0xF8001000
\r
399 #define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115
\r
400 #define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
\r
402 #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
\r
403 #define XPAR_XTTCPS_1_BASEADDR 0xF8001004
\r
404 #define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115
\r
405 #define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
\r
407 #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
\r
408 #define XPAR_XTTCPS_2_BASEADDR 0xF8001008
\r
409 #define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115
\r
410 #define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
\r
413 /******************************************************************/
\r
415 /* Definitions for driver UARTPS */
\r
416 #define XPAR_XUARTPS_NUM_INSTANCES 1
\r
418 /* Definitions for peripheral PS7_UART_1 */
\r
419 #define XPAR_PS7_UART_1_DEVICE_ID 0
\r
420 #define XPAR_PS7_UART_1_BASEADDR 0xE0001000
\r
421 #define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
\r
422 #define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
\r
423 #define XPAR_PS7_UART_1_HAS_MODEM 0
\r
426 /******************************************************************/
\r
428 /* Canonical definitions for peripheral PS7_UART_1 */
\r
429 #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
\r
430 #define XPAR_XUARTPS_0_BASEADDR 0xE0001000
\r
431 #define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
\r
432 #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
\r
433 #define XPAR_XUARTPS_0_HAS_MODEM 0
\r
436 /******************************************************************/
\r
438 /* Definitions for driver USBPS */
\r
439 #define XPAR_XUSBPS_NUM_INSTANCES 1
\r
441 /* Definitions for peripheral PS7_USB_0 */
\r
442 #define XPAR_PS7_USB_0_DEVICE_ID 0
\r
443 #define XPAR_PS7_USB_0_BASEADDR 0xE0002000
\r
444 #define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
\r
447 /******************************************************************/
\r
449 /* Canonical definitions for peripheral PS7_USB_0 */
\r
450 #define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
\r
451 #define XPAR_XUSBPS_0_BASEADDR 0xE0002000
\r
452 #define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
\r
455 /******************************************************************/
\r
457 /* Definitions for driver XADCPS */
\r
458 #define XPAR_XADCPS_NUM_INSTANCES 1
\r
460 /* Definitions for peripheral PS7_XADC_0 */
\r
461 #define XPAR_PS7_XADC_0_DEVICE_ID 0
\r
462 #define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
\r
463 #define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
\r
466 /******************************************************************/
\r
468 /* Canonical definitions for peripheral PS7_XADC_0 */
\r
469 #define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
\r
470 #define XPAR_XADCPS_0_BASEADDR 0xF8007100
\r
471 #define XPAR_XADCPS_0_HIGHADDR 0xF8007120
\r
474 /******************************************************************/
\r
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