1 /* Definition for CPU ID */
\r
2 #define XPAR_CPU_ID 0
\r
4 /* Definitions for peripheral PS7_CORTEXA9_0 */
\r
5 #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
\r
8 /******************************************************************/
\r
10 /* Canonical definitions for peripheral PS7_CORTEXA9_0 */
\r
11 #define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
\r
14 /******************************************************************/
\r
16 #include "xparameters_ps.h"
\r
18 #define STDIN_BASEADDRESS 0xE0001000
\r
19 #define STDOUT_BASEADDRESS 0xE0001000
\r
21 /******************************************************************/
\r
23 /* Definitions for driver CANPS */
\r
24 #define XPAR_XCANPS_NUM_INSTANCES 1
\r
26 /* Definitions for peripheral PS7_CAN_0 */
\r
27 #define XPAR_PS7_CAN_0_DEVICE_ID 0
\r
28 #define XPAR_PS7_CAN_0_BASEADDR 0xE0008000
\r
29 #define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF
\r
30 #define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523
\r
33 /******************************************************************/
\r
35 /* Canonical definitions for peripheral PS7_CAN_0 */
\r
36 #define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID
\r
37 #define XPAR_XCANPS_0_BASEADDR 0xE0008000
\r
38 #define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF
\r
39 #define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523
\r
42 /******************************************************************/
\r
44 /* Definitions for driver DEVCFG */
\r
45 #define XPAR_XDCFG_NUM_INSTANCES 1
\r
47 /* Definitions for peripheral PS7_DEV_CFG_0 */
\r
48 #define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
\r
49 #define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
\r
50 #define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
\r
53 /******************************************************************/
\r
55 /* Canonical definitions for peripheral PS7_DEV_CFG_0 */
\r
56 #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
\r
57 #define XPAR_XDCFG_0_BASEADDR 0xF8007000
\r
58 #define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
\r
61 /******************************************************************/
\r
63 /* Definitions for driver DMAPS */
\r
64 #define XPAR_XDMAPS_NUM_INSTANCES 2
\r
66 /* Definitions for peripheral PS7_DMA_NS */
\r
67 #define XPAR_PS7_DMA_NS_DEVICE_ID 0
\r
68 #define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
\r
69 #define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
\r
72 /* Definitions for peripheral PS7_DMA_S */
\r
73 #define XPAR_PS7_DMA_S_DEVICE_ID 1
\r
74 #define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
\r
75 #define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
\r
78 /******************************************************************/
\r
80 /* Canonical definitions for peripheral PS7_DMA_NS */
\r
81 #define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
\r
82 #define XPAR_XDMAPS_0_BASEADDR 0xF8004000
\r
83 #define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
\r
85 /* Canonical definitions for peripheral PS7_DMA_S */
\r
86 #define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
\r
87 #define XPAR_XDMAPS_1_BASEADDR 0xF8003000
\r
88 #define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
\r
91 /******************************************************************/
\r
93 /* Definitions for driver EMACPS */
\r
94 #define XPAR_XEMACPS_NUM_INSTANCES 1
\r
96 /* Definitions for peripheral PS7_ETHERNET_0 */
\r
97 #define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
\r
98 #define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
\r
99 #define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
\r
100 #define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000
\r
101 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
\r
102 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
\r
103 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
\r
104 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
\r
105 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
\r
106 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
\r
109 /******************************************************************/
\r
111 /* Canonical definitions for peripheral PS7_ETHERNET_0 */
\r
112 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
\r
113 #define XPAR_XEMACPS_0_BASEADDR 0xE000B000
\r
114 #define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
\r
115 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000
\r
116 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
\r
117 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
\r
118 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
\r
119 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
\r
120 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
\r
121 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
\r
124 /******************************************************************/
\r
127 /* Definitions for peripheral PS7_AFI_0 */
\r
128 #define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
\r
129 #define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
\r
132 /* Definitions for peripheral PS7_AFI_1 */
\r
133 #define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
\r
134 #define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
\r
137 /* Definitions for peripheral PS7_AFI_2 */
\r
138 #define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
\r
139 #define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
\r
142 /* Definitions for peripheral PS7_AFI_3 */
\r
143 #define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
\r
144 #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
\r
147 /* Definitions for peripheral PS7_CORESIGHT_COMP_0 */
\r
148 #define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000
\r
149 #define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF
\r
152 /* Definitions for peripheral PS7_DDR_0 */
\r
153 #define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
\r
154 #define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
\r
157 /* Definitions for peripheral PS7_DDRC_0 */
\r
158 #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
\r
159 #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
\r
162 /* Definitions for peripheral PS7_GLOBALTIMER_0 */
\r
163 #define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
\r
164 #define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
\r
167 /* Definitions for peripheral PS7_GPV_0 */
\r
168 #define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
\r
169 #define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
\r
172 /* Definitions for peripheral PS7_INTC_DIST_0 */
\r
173 #define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
\r
174 #define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
\r
177 /* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
\r
178 #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
\r
179 #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
\r
182 /* Definitions for peripheral PS7_L2CACHEC_0 */
\r
183 #define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
\r
184 #define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
\r
187 /* Definitions for peripheral PS7_OCMC_0 */
\r
188 #define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
\r
189 #define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
\r
192 /* Definitions for peripheral PS7_PL310_0 */
\r
193 #define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
\r
194 #define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
\r
197 /* Definitions for peripheral PS7_PMU_0 */
\r
198 #define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
\r
199 #define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
\r
200 #define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
\r
201 #define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
\r
204 /* Definitions for peripheral PS7_QSPI_LINEAR_0 */
\r
205 #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
\r
206 #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
\r
209 /* Definitions for peripheral PS7_RAM_0 */
\r
210 #define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
\r
211 #define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
\r
214 /* Definitions for peripheral PS7_RAM_1 */
\r
215 #define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
\r
216 #define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
\r
219 /* Definitions for peripheral PS7_SCUC_0 */
\r
220 #define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
\r
221 #define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
\r
224 /* Definitions for peripheral PS7_SLCR_0 */
\r
225 #define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
\r
226 #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
\r
229 /******************************************************************/
\r
231 /* Definitions for driver GPIOPS */
\r
232 #define XPAR_XGPIOPS_NUM_INSTANCES 1
\r
234 /* Definitions for peripheral PS7_GPIO_0 */
\r
235 #define XPAR_PS7_GPIO_0_DEVICE_ID 0
\r
236 #define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
\r
237 #define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
\r
240 /******************************************************************/
\r
242 /* Canonical definitions for peripheral PS7_GPIO_0 */
\r
243 #define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
\r
244 #define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
\r
245 #define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
\r
248 /******************************************************************/
\r
250 /* Definitions for driver IICPS */
\r
251 #define XPAR_XIICPS_NUM_INSTANCES 1
\r
253 /* Definitions for peripheral PS7_I2C_0 */
\r
254 #define XPAR_PS7_I2C_0_DEVICE_ID 0
\r
255 #define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
\r
256 #define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
\r
257 #define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
\r
260 /******************************************************************/
\r
262 /* Canonical definitions for peripheral PS7_I2C_0 */
\r
263 #define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
\r
264 #define XPAR_XIICPS_0_BASEADDR 0xE0004000
\r
265 #define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
\r
266 #define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
\r
269 /******************************************************************/
\r
271 /* Definitions for driver QSPIPS */
\r
272 #define XPAR_XQSPIPS_NUM_INSTANCES 1
\r
274 /* Definitions for peripheral PS7_QSPI_0 */
\r
275 #define XPAR_PS7_QSPI_0_DEVICE_ID 0
\r
276 #define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
\r
277 #define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
\r
278 #define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
\r
279 #define XPAR_PS7_QSPI_0_QSPI_MODE 0
\r
282 /******************************************************************/
\r
284 /* Canonical definitions for peripheral PS7_QSPI_0 */
\r
285 #define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
\r
286 #define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
\r
287 #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
\r
288 #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
\r
289 #define XPAR_XQSPIPS_0_QSPI_MODE 0
\r
292 /******************************************************************/
\r
295 /***Definitions for Core_nIRQ/nFIQ interrupts ****/
\r
296 /* Definitions for driver SCUGIC */
\r
297 #define XPAR_XSCUGIC_NUM_INSTANCES 1
\r
299 /* Definitions for peripheral PS7_SCUGIC_0 */
\r
300 #define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
\r
301 #define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
\r
302 #define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
\r
303 #define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
\r
306 /******************************************************************/
\r
308 /* Canonical definitions for peripheral PS7_SCUGIC_0 */
\r
309 #define XPAR_SCUGIC_0_DEVICE_ID 0
\r
310 #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
\r
311 #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
\r
312 #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
\r
315 /******************************************************************/
\r
317 /* Definitions for driver SCUTIMER */
\r
318 #define XPAR_XSCUTIMER_NUM_INSTANCES 1
\r
320 /* Definitions for peripheral PS7_SCUTIMER_0 */
\r
321 #define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
\r
322 #define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
\r
323 #define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
\r
326 /******************************************************************/
\r
328 /* Canonical definitions for peripheral PS7_SCUTIMER_0 */
\r
329 #define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
\r
330 #define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
\r
331 #define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
\r
334 /******************************************************************/
\r
336 /* Definitions for driver SCUWDT */
\r
337 #define XPAR_XSCUWDT_NUM_INSTANCES 1
\r
339 /* Definitions for peripheral PS7_SCUWDT_0 */
\r
340 #define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
\r
341 #define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
\r
342 #define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
\r
345 /******************************************************************/
\r
347 /* Canonical definitions for peripheral PS7_SCUWDT_0 */
\r
348 #define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
\r
349 #define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
\r
350 #define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
\r
353 /******************************************************************/
\r
355 /* Definitions for driver SDPS */
\r
356 #define XPAR_XSDPS_NUM_INSTANCES 1
\r
358 /* Definitions for peripheral PS7_SD_0 */
\r
359 #define XPAR_PS7_SD_0_DEVICE_ID 0
\r
360 #define XPAR_PS7_SD_0_BASEADDR 0xE0100000
\r
361 #define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
\r
362 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
\r
365 /******************************************************************/
\r
367 /* Canonical definitions for peripheral PS7_SD_0 */
\r
368 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
\r
369 #define XPAR_XSDPS_0_BASEADDR 0xE0100000
\r
370 #define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
\r
371 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
\r
374 /******************************************************************/
\r
376 /* Definitions for driver TTCPS */
\r
377 #define XPAR_XTTCPS_NUM_INSTANCES 3
\r
379 /* Definitions for peripheral PS7_TTC_0 */
\r
380 #define XPAR_PS7_TTC_0_DEVICE_ID 0
\r
381 #define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
\r
382 #define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
\r
383 #define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
\r
384 #define XPAR_PS7_TTC_1_DEVICE_ID 1
\r
385 #define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
\r
386 #define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
\r
387 #define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
\r
388 #define XPAR_PS7_TTC_2_DEVICE_ID 2
\r
389 #define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
\r
390 #define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
\r
391 #define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
\r
394 /******************************************************************/
\r
396 /* Canonical definitions for peripheral PS7_TTC_0 */
\r
397 #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
\r
398 #define XPAR_XTTCPS_0_BASEADDR 0xF8001000
\r
399 #define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115
\r
400 #define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
\r
402 #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
\r
403 #define XPAR_XTTCPS_1_BASEADDR 0xF8001004
\r
404 #define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115
\r
405 #define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
\r
407 #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
\r
408 #define XPAR_XTTCPS_2_BASEADDR 0xF8001008
\r
409 #define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115
\r
410 #define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
\r
413 /******************************************************************/
\r
415 /* Definitions for driver UARTPS */
\r
416 #define XPAR_XUARTPS_NUM_INSTANCES 1
\r
418 /* Definitions for peripheral PS7_UART_1 */
\r
419 #define XPAR_PS7_UART_1_DEVICE_ID 0
\r
420 #define XPAR_PS7_UART_1_BASEADDR 0xE0001000
\r
421 #define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
\r
422 #define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
\r
423 #define XPAR_PS7_UART_1_HAS_MODEM 0
\r
426 /******************************************************************/
\r
428 /* Canonical definitions for peripheral PS7_UART_1 */
\r
429 #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
\r
430 #define XPAR_XUARTPS_0_BASEADDR 0xE0001000
\r
431 #define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
\r
432 #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
\r
433 #define XPAR_XUARTPS_0_HAS_MODEM 0
\r
436 /******************************************************************/
\r
438 /* Definitions for driver USBPS */
\r
439 #define XPAR_XUSBPS_NUM_INSTANCES 1
\r
441 /* Definitions for peripheral PS7_USB_0 */
\r
442 #define XPAR_PS7_USB_0_DEVICE_ID 0
\r
443 #define XPAR_PS7_USB_0_BASEADDR 0xE0002000
\r
444 #define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
\r
447 /******************************************************************/
\r
449 /* Canonical definitions for peripheral PS7_USB_0 */
\r
450 #define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
\r
451 #define XPAR_XUSBPS_0_BASEADDR 0xE0002000
\r
452 #define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
\r
455 /******************************************************************/
\r
457 /* Definitions for driver XADCPS */
\r
458 #define XPAR_XADCPS_NUM_INSTANCES 1
\r
460 /* Definitions for peripheral PS7_XADC_0 */
\r
461 #define XPAR_PS7_XADC_0_DEVICE_ID 0
\r
462 #define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
\r
463 #define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
\r
466 /******************************************************************/
\r
468 /* Canonical definitions for peripheral PS7_XADC_0 */
\r
469 #define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
\r
470 #define XPAR_XADCPS_0_BASEADDR 0xF8007100
\r
471 #define XPAR_XADCPS_0_HIGHADDR 0xF8007120
\r
474 /******************************************************************/
\r
projects / freertos / blob