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32 /*****************************************************************************/
36 * @addtogroup qspips_v3_0
40 * This file contains the implementation of the XQspiPs driver. It supports only
41 * master mode. User documentation for the driver functions is contained in this
42 * file in the form of comment blocks at the front of each function.
44 * A QSPI device connects to an QSPI bus through a 4-wire serial interface.
45 * The QSPI bus is a full-duplex, synchronous bus that facilitates communication
46 * between one master and one slave. The device is always full-duplex,
47 * which means that for every byte sent, one is received, and vice-versa.
48 * The master controls the clock, so it can regulate when it wants to
49 * send or receive data. The slave is under control of the master, it must
50 * respond quickly since it has no control of the clock and must send/receive
51 * data as fast or as slow as the master does.
53 * <b> Linear Mode </b>
54 * The Linear Quad-SPI Controller extends the existing Quad-SPI Controller
\92s
55 * functionality by adding a linear addressing scheme that allows the SPI flash
56 * memory subsystem to behave like a typical ROM device. The new feature hides
57 * the normal SPI protocol from a master reading from the SPI flash memory. The
58 * feature improves both the user friendliness and the overall read memory
59 * throughput over that of the current Quad-SPI Controller by lessening the
60 * amount of software overheads required and by the use of the faster AXI
63 * <b>Initialization & Configuration</b>
65 * The XQspiPs_Config structure is used by the driver to configure itself. This
66 * configuration structure is typically created by the tool-chain based on HW
69 * To support multiple runtime loading and initialization strategies employed by
70 * various operating systems, the driver instance can be initialized in the
72 * - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
73 * static configuration structure defined in xqspips_g.c. This is setup
74 * by the tools. For some operating systems the config structure will be
75 * initialized by the software and this call is not needed.
76 * - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
77 * configuration structure provided by the caller. If running in a system
78 * with address translation, the provided virtual memory base address
79 * replaces the physical address present in the configuration structure.
81 * <b>Multiple Masters</b>
83 * More than one master can exist, but arbitration is the responsibility of
84 * the higher layer software. The device driver does not perform any type of
87 * <b>Modes of Operation</b>
89 * There are four modes to perform a data transfer and the selection of a mode
90 * is based on Chip Select(CS) and Start. These two options individually, can
91 * be controlled either by software(Manual) or hardware(Auto).
92 * - Auto CS: Chip select is automatically asserted as soon as the first word
93 * is written into the TXFIFO and de asserted when the TXFIFO becomes
95 * - Manual CS: Software must assert and de assert CS.
96 * - Auto Start: Data transmission starts as soon as there is data in the
97 * TXFIFO and stalls when the TXFIFO is empty
98 * - Manual Start: Software must start data transmission at the beginning of
99 * the transaction or whenever the TXFIFO has become empty
101 * The preferred combination is Manual CS and Auto Start.
102 * In this combination, the software asserts CS before loading any data into
103 * TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
104 * out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
105 * data is available. If no further data, software disables CS.
107 * Risks/challenges of other combinations:
108 * - Manual CS and Manual Start: Manual Start bit should be set after each
109 * TXFIFO write otherwise there could be a race condition where the TXFIFO
110 * becomes empty before the new word is written. In that case the
111 * transmission stops.
112 * - Auto CS with Manual or Auto Start: It is very difficult for software to
113 * keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
114 * This results in a single transaction to be split into multiple pieces each
115 * with its own chip select. This will result in garbage data to be sent.
119 * The user must connect the interrupt handler of the driver,
120 * XQspiPs_InterruptHandler, to an interrupt system such that it will be
121 * called when an interrupt occurs. This function does not save and restore
122 * the processor context such that the user must provide this processing.
124 * The driver handles the following interrupts:
125 * - Data Transmit Register/FIFO Underflow
126 * - Data Receive Register/FIFO Not Empty
127 * - Data Transmit Register/FIFO Overwater
128 * - Data Receive Register/FIFO Overrun
130 * The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
131 * QSPI device has transmitted the data available to transmit, and now its data
132 * register and FIFO is ready to accept more data. The driver uses this
133 * interrupt to indicate progress while sending data. The driver may have
134 * more data to send, in which case the data transmit register and FIFO is
135 * filled for subsequent transmission. When this interrupt arrives and all
136 * the data has been sent, the driver invokes the status callback with a
137 * value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
138 * all data has been sent.
140 * The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
141 * as slave, the QSPI device was required to transmit but there was no data
142 * available to transmit in the transmit register (or FIFO). This may not
143 * be an error if the master is not expecting data. But in the case where
144 * the master is expecting data, this serves as a notification of such a
145 * condition. The driver reports this condition to the upper layer
146 * software through the status handler.
148 * The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
149 * device received data and subsequently dropped the data because the data
150 * receive register and FIFO was full. The driver reports this condition to the
151 * upper layer software through the status handler. This likely indicates a
152 * problem with the higher layer protocol, or a problem with the slave
156 * <b>Polled Operation</b>
158 * Transfer in polled mode is supported through a separate interface function
159 * XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
160 * this function blocks until all data has been sent/received.
164 * Some operations are disallowed when the device is busy. The driver tracks
165 * whether a device is busy. The device is considered busy when a data transfer
166 * request is outstanding, and is considered not busy only when that transfer
167 * completes (or is aborted with a mode fault error).
169 * <b>Device Configuration</b>
171 * The device can be configured in various ways during the FPGA implementation
172 * process. Configuration parameters are stored in the xqspips_g.c file or
173 * passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
174 * contains configuration information for an QSPI device, including the base
175 * address for the device.
177 * <b>RTOS Independence</b>
179 * This driver is intended to be RTOS and processor independent. It works with
180 * physical addresses only. Any needs for dynamic memory management, threads or
181 * thread mutual exclusion, virtual memory, or cache control must be satisfied
182 * by the layer above this driver.
184 * NOTE: This driver was always tested with endianess set to little-endian.
187 * MODIFICATION HISTORY:
189 * Ver Who Date Changes
190 * ----- --- -------- -----------------------------------------------
191 * 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
192 * 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
194 * 2.00a kka 07/25/12 Added a few register defines for CR 670297
195 * Removed code related to mode fault for CR 671468
196 * The XQspiPs_SetSlaveSelect has been modified to remove
197 * the argument of the slave select as the QSPI controller
198 * only supports one slave.
199 * XQspiPs_GetSlaveSelect API has been removed
200 * Added a flag ShiftReadData to the instance structure
201 *. and is used in the XQspiPs_GetReadData API.
202 * The ShiftReadData Flag indicates whether the data
203 * read from the Rx FIFO needs to be shifted
204 * in cases where the data is less than 4 bytes
205 * Removed the selection for the following options:
206 * Master mode (XQSPIPS_MASTER_OPTION) and
207 * Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
208 * as the QSPI driver supports the Master mode
209 * and Flash Interface mode and doesnot support
210 * Slave mode or the legacy mode.
211 * Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
212 * APIs so that the last argument (IsInst) specifying whether
213 * it is instruction or data has been removed. The first byte
214 * in the SendBufPtr argument of these APIs specify the
215 * instruction to be sent to the Flash Device.
216 * This version of the driver fixes CRs 670197/663787/
218 * Added the option for setting the Holdb_dr bit in the
219 * configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
220 * is the option to be used for setting this bit in the
221 * configuration register.
222 * The XQspiPs_PolledTransfer function has been updated
223 * to fill the data to fifo depth.
224 * 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
225 * Added macros for Set/Get Rx Watermark. Changed QSPI
226 * Enable/Disable macro argument from BaseAddress to
227 * Instance Pointer. Added DelayNss argument to SetDelays
228 * and GetDelays API's.
229 * Created macros XQspiPs_IsManualStart and
230 * XQspiPs_IsManualChipSelect.
231 * Changed QSPI transfer logic for polled and interrupt
232 * modes to be based on filled tx fifo count and receive
233 * based on it. RXNEMPTY interrupt is not used.
234 * Added assertions to XQspiPs_LqspiRead function.
235 * SetDelays and GetDelays API's include DelayNss parameter.
236 * Added defines for DelayNss,Rx Watermark,Interrupts
237 * which need write to clear. Removed Read zeros mask from
238 * LQSPI Config register. Renamed Fixed burst error to
239 * data FSM error in LQSPI Status register.
241 * 2.02a hk 05/07/13 Added ConnectionMode to config structure.
242 * Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
243 * Added enable and disable to the XQspiPs_LqspiRead() function
244 * Removed XQspi_Reset() in Set_Options() function when
245 * LQSPI_MODE_OPTION is set.
246 * Added instructions for bank selection, die erase and
247 * flag status register to the flash instruction table
248 * Handling for instructions not in flash instruction
249 * table added. Checking for Tx FIFO empty when switching from
250 * TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
251 * byte count 3 (spansion), instruction size and TXD register
252 * changed accordingly. CR# 712502 and 703869.
253 * Added prefix to constant definitions for ConnectionMode
254 * Added (#ifdef linear base address) in the Linear read function.
255 * Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
256 * XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
257 * XQspiPs_LqspiRead function. Fix for CR#718141.
259 * 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
260 * thresholds. This is to improve performance.
261 * Added API's for QSPI reset and
262 * linear mode initialization for boot.
263 * Added RX and TX threshold reset to one in XQspiPs_Abort.
264 * Added RX threshold reset(1) after transfer in polled and
265 * interrupt transfers. Made changes to make sure threshold
266 * change is done only when no transfer is in progress.
267 * Updated linear init API for parallel and stacked modes.
272 ******************************************************************************/
273 #ifndef XQSPIPS_H /* prevent circular inclusions */
274 #define XQSPIPS_H /* by using protection macros */
280 /***************************** Include Files *********************************/
283 #include "xqspips_hw.h"
286 /************************** Constant Definitions *****************************/
288 /** @name Configuration options
290 * The following options are supported to enable/disable certain features of
291 * an QSPI device. Each of the options is a bit mask, so more than one may be
295 * The <b>Active Low Clock option</b> configures the device's clock polarity.
296 * Setting this option means the clock is active low and the SCK signal idles
297 * high. By default, the clock is active high and SCK idles low.
299 * The <b>Clock Phase option</b> configures the QSPI device for one of two
300 * transfer formats. A clock phase of 0, the default, means data is valid on
301 * the first SCK edge (rising or falling) after the slave select (SS) signal
302 * has been asserted. A clock phase of 1 means data is valid on the second SCK
303 * edge (rising or falling) after SS has been asserted.
306 * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
307 * the slave select signal.
308 * 0: The SPI_SS signal is controlled by the QSPI controller during
309 * transfers. (Default)
310 * 1: The SPI_SS signal is forced active (driven low) regardless of any
311 * transfers in progress.
313 * NOTE: The driver will handle setting and clearing the Slave Select when
314 * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
315 * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
316 * processor cannot empty and refill the FIFOs before the TX FIFO is empty
317 * When the QSPI hardware is controlling the Slave Select signals, this
318 * will cause slave to be de-selected and terminate the transfer.
320 * The <b>Manual Start option</b> is used to enable manual control of
321 * the Start command to perform data transfer.
322 * 0: The Start command is controlled by the QSPI controller during
323 * transfers(Default). Data transmission starts as soon as there is data in
324 * the TXFIFO and stalls when the TXFIFO is empty
325 * 1: The Start command must be issued by software to perform data transfer.
326 * Bit 15 of Configuration register is used to issue Start command. This bit
327 * must be set whenever TXFIFO is filled with new data.
329 * NOTE: The driver will set the Manual Start Enable bit in Configuration
330 * Register, if Manual Start option is selected. Software will issue
331 * Manual Start command whenever TXFIFO is filled with data. When there is
332 * no further data, driver will clear the Manual Start Enable bit.
336 #define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
337 #define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
338 #define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
339 #define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
340 #define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
341 #define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
345 /** @name QSPI Clock Prescaler options
346 * The QSPI Clock Prescaler Configuration bits are used to program master mode
347 * bit rate. The bit rate can be programmed in divide-by-two decrements from
348 * pclk/2 to pclk/256.
352 #define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
353 #define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
354 #define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
355 #define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
356 #define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
357 #define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
358 #define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
359 #define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
364 /** @name Callback events
366 * These constants specify the handler events that are passed to
367 * a handler from the driver. These constants are not bit masks such that
368 * only one will be passed at a time to the handler.
372 #define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
373 #define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
374 #define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
378 /** @name Flash commands
380 * The following constants define most of the commands supported by flash
381 * devices. Users can add more commands supported by the flash devices
385 #define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
386 #define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
387 #define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
388 #define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
389 #define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
390 #define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
391 #define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
392 #define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
393 #define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
394 #define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
395 #define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
396 #define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
397 #define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
398 #define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
399 #define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
400 #define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
401 #define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
402 #define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
403 #define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
404 #define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
405 #define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
406 /* Extende Address Register Write - Micron's equivalent of Bank Register */
407 #define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
408 /* Extende Address Register Read - Micron's equivalent of Bank Register */
409 #define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
410 #define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
411 #define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
412 #define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
413 #define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */
414 #define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */
418 /** @name Instruction size
420 * The following constants define numbers 1 to 4.
421 * Used to identify whether TXD0,1,2 or 3 is to be used.
425 #define XQSPIPS_SIZE_ONE 1
426 #define XQSPIPS_SIZE_TWO 2
427 #define XQSPIPS_SIZE_THREE 3
428 #define XQSPIPS_SIZE_FOUR 4
432 /** @name ConnectionMode
434 * The following constants are the possible values of ConnectionMode in
439 #define XQSPIPS_CONNECTION_MODE_SINGLE 0
440 #define XQSPIPS_CONNECTION_MODE_STACKED 1
441 #define XQSPIPS_CONNECTION_MODE_PARALLEL 2
445 /** @name FIFO threshold value
447 * This is the Rx FIFO threshold (in words) that was found to be most
448 * optimal in terms of performance
452 #define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
456 /**************************** Type Definitions *******************************/
458 * The handler data type allows the user to define a callback function to
459 * handle the asynchronous processing for the QSPI device. The application
460 * using this driver is expected to define a handler of this type to support
461 * interrupt driven mode. The handler executes in an interrupt context, so
462 * only minimal processing should be performed.
464 * @param CallBackRef is the callback reference passed in by the upper
465 * layer when setting the callback functions, and passed back to
466 * the upper layer when the callback is invoked. Its type is
467 * not important to the driver, so it is a void pointer.
468 * @param StatusEvent holds one or more status events that have occurred.
469 * See the XQspiPs_SetStatusHandler() for details on the status
470 * events that can be passed in the callback.
471 * @param ByteCount indicates how many bytes of data were successfully
472 * transferred. This may be less than the number of bytes
473 * requested if the status event indicates an error.
475 typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
479 * This typedef contains configuration information for the device.
482 u16 DeviceId; /**< Unique ID of device */
483 u32 BaseAddress; /**< Base address of the device */
484 u32 InputClockHz; /**< Input clock frequency */
485 u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
489 * The XQspiPs driver instance data. The user is required to allocate a
490 * variable of this type for every QSPI device in the system. A pointer
491 * to a variable of this type is then passed to the driver API functions.
494 XQspiPs_Config Config; /**< Configuration structure */
495 u32 IsReady; /**< Device is initialized and ready */
497 u8 *SendBufferPtr; /**< Buffer to send (state) */
498 u8 *RecvBufferPtr; /**< Buffer to receive (state) */
499 int RequestedBytes; /**< Number of bytes to transfer (state) */
500 int RemainingBytes; /**< Number of bytes left to transfer(state) */
501 u32 IsBusy; /**< A transfer is in progress (state) */
502 XQspiPs_StatusHandler StatusHandler;
503 void *StatusRef; /**< Callback reference for status handler */
504 u32 ShiftReadData; /**< Flag to indicate whether the data
505 * read from the Rx FIFO needs to be shifted
506 * in cases where the data is less than 4
511 /***************** Macros (Inline Functions) Definitions *********************/
513 /****************************************************************************/
516 * Check in OptionsTable if Manual Start Option is enabled or disabled.
518 * @param InstancePtr is a pointer to the XQspiPs instance.
521 * - TRUE if option is set
522 * - FALSE if option is not set
524 * @note C-Style signature:
525 * u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
527 *****************************************************************************/
528 #define XQspiPs_IsManualStart(InstancePtr) \
529 ((XQspiPs_GetOptions(InstancePtr) & \
530 XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
532 /****************************************************************************/
535 * Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
537 * @param InstancePtr is a pointer to the XSpiPs instance.
540 * - TRUE if option is set
541 * - FALSE if option is not set
543 * @note C-Style signature:
544 * u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
546 *****************************************************************************/
547 #define XQspiPs_IsManualChipSelect(InstancePtr) \
548 ((XQspiPs_GetOptions(InstancePtr) & \
549 XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
551 /****************************************************************************/
554 * Set the contents of the slave idle count register.
556 * @param InstancePtr is a pointer to the XQspiPs instance.
557 * @param RegisterValue is the value to be written, valid values are
564 * void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
566 *****************************************************************************/
567 #define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
568 XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
569 XQSPIPS_SICR_OFFSET, (RegisterValue))
571 /****************************************************************************/
574 * Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
575 * constants defined in xqspips_hw.h to interpret the bit-mask returned.
577 * @param InstancePtr is a pointer to the XQspiPs instance.
579 * @return An 8-bit value representing Slave Idle Count.
581 * @note C-Style signature:
582 * u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
584 *****************************************************************************/
585 #define XQspiPs_GetSlaveIdle(InstancePtr) \
586 XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
589 /****************************************************************************/
592 * Set the contents of the transmit FIFO watermark register.
594 * @param InstancePtr is a pointer to the XQspiPs instance.
595 * @param RegisterValue is the value to be written, valid values are 1-63.
601 * void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
603 *****************************************************************************/
604 #define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
605 XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
606 XQSPIPS_TXWR_OFFSET, (RegisterValue))
608 /****************************************************************************/
611 * Get the contents of the transmit FIFO watermark register.
612 * Valid values are in the range 1-63.
614 * @param InstancePtr is a pointer to the XQspiPs instance.
616 * @return A 6-bit value representing Tx Watermark level.
618 * @note C-Style signature:
619 * u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
621 *****************************************************************************/
622 #define XQspiPs_GetTXWatermark(InstancePtr) \
623 XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
625 /****************************************************************************/
628 * Set the contents of the receive FIFO watermark register.
630 * @param InstancePtr is a pointer to the XQspiPs instance.
631 * @param RegisterValue is the value to be written, valid values are 1-63.
637 * void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
639 *****************************************************************************/
640 #define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
641 XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
642 XQSPIPS_RXWR_OFFSET, (RegisterValue))
644 /****************************************************************************/
647 * Get the contents of the receive FIFO watermark register.
648 * Valid values are in the range 1-63.
650 * @param InstancePtr is a pointer to the XQspiPs instance.
652 * @return A 6-bit value representing Rx Watermark level.
654 * @note C-Style signature:
655 * u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
657 *****************************************************************************/
658 #define XQspiPs_GetRXWatermark(InstancePtr) \
659 XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
661 /****************************************************************************/
664 * Enable the device and uninhibit master transactions.
666 * @param InstancePtr is a pointer to the XQspiPs instance.
670 * @note C-Style signature:
671 * void XQspiPs_Enable(XQspiPs *InstancePtr)
673 *****************************************************************************/
674 #define XQspiPs_Enable(InstancePtr) \
675 XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
676 XQSPIPS_ER_ENABLE_MASK)
678 /****************************************************************************/
681 * Disable the device.
683 * @param InstancePtr is a pointer to the XQspiPs instance.
687 * @note C-Style signature:
688 * void XQspiPs_Disable(XQspiPs *InstancePtr)
690 *****************************************************************************/
691 #define XQspiPs_Disable(InstancePtr) \
692 XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
694 /****************************************************************************/
697 * Set the contents of the Linear QSPI Configuration register.
699 * @param InstancePtr is a pointer to the XQspiPs instance.
700 * @param RegisterValue is the value to be written to the Linear QSPI
701 * configuration register.
707 * void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
710 *****************************************************************************/
711 #define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
712 XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
713 XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
715 /****************************************************************************/
718 * Get the contents of the Linear QSPI Configuration register.
720 * @param InstancePtr is a pointer to the XQspiPs instance.
722 * @return A 32-bit value representing the contents of the LQSPI Config
725 * @note C-Style signature:
726 * u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
728 *****************************************************************************/
729 #define XQspiPs_GetLqspiConfigReg(InstancePtr) \
730 XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
731 XQSPIPS_LQSPI_CR_OFFSET)
733 /************************** Function Prototypes ******************************/
736 * Initialization function, implemented in xqspips_sinit.c
738 XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
741 * Functions implemented in xqspips.c
743 int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
745 void XQspiPs_Reset(XQspiPs *InstancePtr);
746 void XQspiPs_Abort(XQspiPs *InstancePtr);
748 int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
750 int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
751 u8 *RecvBufPtr, unsigned ByteCount);
752 int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
753 u32 Address, unsigned ByteCount);
755 int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
757 void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
758 XQspiPs_StatusHandler FuncPtr);
759 void XQspiPs_InterruptHandler(void *InstancePtr);
762 * Functions for selftest, in xqspips_selftest.c
764 int XQspiPs_SelfTest(XQspiPs *InstancePtr);
767 * Functions for options, in xqspips_options.c
769 int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
770 u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
772 int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
773 u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
775 int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
776 u8 DelayAfter, u8 DelayInit);
777 void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
778 u8 *DelayAfter, u8 *DelayInit);
783 #endif /* end of protection macro */