1 /******************************************************************************
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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This header file contains the identifiers and basic HW access driver
38 * functions (or macros) that can be used to access the device. Other driver
39 * functions are defined in xqspips.h.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- --- -------- -----------------------------------------------
46 * 1.00 sdm 11/25/10 First release
47 * 2.00a ka 07/25/12 Added a few register defines for CR 670297
48 * and removed some defines of reserved fields for
50 * Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
51 * bit in Configuration register.
52 * 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
53 * which need write to clear. Removed Read zeros mask from
54 * LQSPI Config register.
55 * 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
56 * linear mode initialization for boot. Added related
57 * constant definitions.
61 ******************************************************************************/
62 #ifndef XQSPIPS_HW_H /* prevent circular inclusions */
63 #define XQSPIPS_HW_H /* by using protection macros */
69 /***************************** Include Files *********************************/
71 #include "xil_types.h"
72 #include "xil_assert.h"
74 #include "xparameters.h"
76 /************************** Constant Definitions *****************************/
78 /** @name Register Map
80 * Register offsets from the base address of an QSPI device.
83 #define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
84 #define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
85 #define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
86 #define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
87 #define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
88 #define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
89 #define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
90 #define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
91 #define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
92 #define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
93 #define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
94 #define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
95 #define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
96 #define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
97 #define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
98 #define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
99 #define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
100 #define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
101 #define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
102 #define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
106 /** @name Configuration Register
108 * This register contains various control bits that
109 * affect the operation of the QSPI device. Read/Write.
113 #define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
114 #define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
115 #define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
116 #define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
118 #define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
119 #define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
120 #define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
121 #define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
123 #define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
124 #define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
125 #define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
127 #define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
128 #define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
130 #define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
132 #define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
134 /* Deselect the Slave select line and set the transfer size to 32 at reset */
135 #define XQSPIPS_CR_RESET_STATE (XQSPIPS_CR_IFMODE_MASK | \
136 XQSPIPS_CR_SSCTRL_MASK | \
137 XQSPIPS_CR_DATA_SZ_MASK | \
138 XQSPIPS_CR_MSTREN_MASK)
142 /** @name QSPI Interrupt Registers
144 * <b>QSPI Status Register</b>
146 * This register holds the interrupt status flags for an QSPI device. Some
147 * of the flags are level triggered, which means that they are set as long
148 * as the interrupt condition exists. Other flags are edge triggered,
149 * which means they are set once the interrupt condition occurs and remain
150 * set until they are cleared by software. The interrupts are cleared by
151 * writing a '1' to the interrupt bit position in the Status Register.
154 * <b>QSPI Interrupt Enable Register</b>
156 * This register is used to enable chosen interrupts for an QSPI device.
157 * Writing a '1' to a bit in this register sets the corresponding bit in the
158 * QSPI Interrupt Mask register. Write only.
160 * <b>QSPI Interrupt Disable Register </b>
162 * This register is used to disable chosen interrupts for an QSPI device.
163 * Writing a '1' to a bit in this register clears the corresponding bit in the
164 * QSPI Interrupt Mask register. Write only.
166 * <b>QSPI Interrupt Mask Register</b>
168 * This register shows the enabled/disabled interrupts of an QSPI device.
171 * All four registers have the same bit definitions. They are only defined once
172 * for each of the Interrupt Enable Register, Interrupt Disable Register,
173 * Interrupt Mask Register, and Channel Interrupt Status Register
177 #define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
178 #define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
179 #define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
180 #define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
181 #define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
182 #define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
183 #define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
185 #define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
186 need write to clear */
187 #define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
188 #define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
192 /** @name Enable Register
194 * This register is used to enable or disable an QSPI device.
198 #define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
202 /** @name Delay Register
204 * This register is used to program timing delays in
205 * slave mode. Read/Write
208 #define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
209 between two words mask */
210 #define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
211 between two words shift */
212 #define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
214 #define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
215 #define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
216 #define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
217 #define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
220 /** @name Slave Idle Count Registers
222 * This register defines the number of pclk cycles the slave waits for a the
223 * QSPI clock to become stable in quiescent state before it can detect the start
224 * of the next transfer in CPHA = 1 mode.
229 #define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
233 /** @name Transmit FIFO Watermark Register
235 * This register defines the watermark setting for the Transmit FIFO.
239 #define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
240 #define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
241 * register reset value */
245 /** @name Receive FIFO Watermark Register
247 * This register defines the watermark setting for the Receive FIFO.
251 #define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
252 #define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
253 * register reset value */
259 * This macro provides the depth of transmit FIFO and receive FIFO.
263 #define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
267 /** @name Linear QSPI Configuration Register
269 * This register contains various control bits that
270 * affect the operation of the Linear QSPI controller. Read/Write.
274 #define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
275 #define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
276 #define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */
277 #define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
278 #define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
279 #define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
280 #define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
282 #define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
283 between addr and return
285 #define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
286 #define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
289 /** @name Linear QSPI Status Register
291 * This register contains various status bits of the Linear QSPI controller.
296 #define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
298 #define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
303 /** @name Loopback Delay Adjust Register
305 * This register contains various bit masks of Loopback Delay Adjust Register.
310 #define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
315 /**************************** Type Definitions *******************************/
317 /***************** Macros (Inline Functions) Definitions *********************/
319 #define XQspiPs_In32 Xil_In32
320 #define XQspiPs_Out32 Xil_Out32
322 /****************************************************************************/
326 * @param BaseAddress contains the base address of the device.
327 * @param RegOffset contains the offset from the 1st register of the
328 * device to the target register.
330 * @return The value read from the register.
332 * @note C-Style signature:
333 * u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
335 ******************************************************************************/
336 #define XQspiPs_ReadReg(BaseAddress, RegOffset) \
337 XQspiPs_In32((BaseAddress) + (RegOffset))
339 /***************************************************************************/
341 * Write to a register.
343 * @param BaseAddress contains the base address of the device.
344 * @param RegOffset contains the offset from the 1st register of the
345 * device to target register.
346 * @param RegisterValue is the value to be written to the register.
350 * @note C-Style signature:
351 * void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
354 ******************************************************************************/
355 #define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
356 XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
358 /************************** Function Prototypes ******************************/
361 * Functions implemented in xqspips_hw.c
363 void XQspiPs_ResetHw(u32 BaseAddress);
364 void XQspiPs_LinearInit(u32 BaseAddress);
366 /************************** Variable Definitions *****************************/
372 #endif /* end of protection macro */