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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This header file contains identifiers and HW access functions (or
38 * macros) that can be used to access the device. The user should refer to the
39 * hardware device specification for more details of the device operation.
40 * The driver functions/APIs are defined in xscugic.h.
42 * This GIC device has two parts, a distributor and CPU interface(s). Each part
43 * has separate register definition sections.
47 * MODIFICATION HISTORY:
49 * Ver Who Date Changes
50 * ----- ---- -------- -----------------------------------------------------
51 * 1.00a drg 01/19/10 First release
52 * 1.01a sdm 11/09/11 "xil_exception.h" added as include.
53 * Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
54 * added to enable or disable interrupts based on
55 * Distributor Register base address. Normally users use
56 * XScuGic instance and call XScuGic_Enable or
57 * XScuGic_Disable to enable/disable interrupts. These
58 * new macros are provided when user does not want to
59 * use an instance pointer but still wants to enable or
61 * Function prototypes for functions (present in newly
62 * added file xscugic_hw.c) are added.
63 * 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
65 * 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
66 * XScuGic_SetPriTrigTypeByDistAddr and
67 * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
71 ******************************************************************************/
73 #ifndef XSCUGIC_HW_H /* prevent circular inclusions */
74 #define XSCUGIC_HW_H /* by using protection macros */
80 /***************************** Include Files *********************************/
82 #include "xil_types.h"
83 #include "xil_assert.h"
85 #include "xil_exception.h"
87 /************************** Constant Definitions *****************************/
90 * The maximum number of interrupts supported by the hardware.
92 #define XSCUGIC_MAX_NUM_INTR_INPUTS 95
95 * The maximum priority value that can be used in the GIC.
97 #define XSCUGIC_MAX_INTR_PRIO_VAL 248
98 #define XSCUGIC_INTR_PRIO_MASK 0xF8
100 /** @name Distributor Interface Register Map
102 * Define the offsets from the base address for all Distributor registers of
103 * the interrupt controller, some registers may be reserved in the hardware
107 #define XSCUGIC_DIST_EN_OFFSET 0x00000000 /**< Distributor Enable
109 #define XSCUGIC_IC_TYPE_OFFSET 0x00000004 /**< Interrupt Controller
111 #define XSCUGIC_DIST_IDENT_OFFSET 0x00000008 /**< Implementor ID
113 #define XSCUGIC_SECURITY_OFFSET 0x00000080 /**< Interrupt Security
115 #define XSCUGIC_ENABLE_SET_OFFSET 0x00000100 /**< Enable Set
117 #define XSCUGIC_DISABLE_OFFSET 0x00000180 /**< Enable Clear Register */
118 #define XSCUGIC_PENDING_SET_OFFSET 0x00000200 /**< Pending Set
120 #define XSCUGIC_PENDING_CLR_OFFSET 0x00000280 /**< Pending Clear
122 #define XSCUGIC_ACTIVE_OFFSET 0x00000300 /**< Active Status Register */
123 #define XSCUGIC_PRIORITY_OFFSET 0x00000400 /**< Priority Level Register */
124 #define XSCUGIC_SPI_TARGET_OFFSET 0x00000800 /**< SPI Target
125 Register 0x800-0x8FB */
126 #define XSCUGIC_INT_CFG_OFFSET 0x00000C00 /**< Interrupt Configuration
127 Register 0xC00-0xCFC */
128 #define XSCUGIC_PPI_STAT_OFFSET 0x00000D00 /**< PPI Status Register */
129 #define XSCUGIC_SPI_STAT_OFFSET 0x00000D04 /**< SPI Status Register
131 #define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80 /**< AHB Configuration
133 #define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00 /**< Software Triggered
134 Interrupt Register */
135 #define XSCUGIC_PERPHID_OFFSET 0x00000FD0 /**< Peripheral ID Reg */
136 #define XSCUGIC_PCELLID_OFFSET 0x00000FF0 /**< Pcell ID Register */
139 /** @name Distributor Enable Register
140 * Controls if the distributor response to external interrupt inputs.
143 #define XSCUGIC_EN_INT_MASK 0x00000001 /**< Interrupt In Enable */
146 /** @name Interrupt Controller Type Register
149 #define XSCUGIC_LSPI_MASK 0x0000F800 /**< Number of Lockable
152 #define XSCUGIC_DOMAIN_MASK 0x00000400 /**< Number os Security domains*/
153 #define XSCUGIC_CPU_NUM_MASK 0x000000E0 /**< Number of CPU Interfaces */
154 #define XSCUGIC_NUM_INT_MASK 0x0000001F /**< Number of Interrupt IDs */
157 /** @name Implementor ID Register
158 * Implementor and revision information.
161 #define XSCUGIC_REV_MASK 0x00FFF000 /**< Revision Number */
162 #define XSCUGIC_IMPL_MASK 0x00000FFF /**< Implementor */
165 /** @name Interrupt Security Registers
166 * Each bit controls the security level of an interrupt, either secure or non
167 * secure. These registers can only be accessed using secure read and write.
168 * There are registers for each of the CPU interfaces at offset 0x080. A
169 * register set for the SPI interrupts is available to all CPU interfaces.
170 * There are up to 32 of these registers staring at location 0x084.
173 #define XSCUGIC_INT_NS_MASK 0x00000001 /**< Each bit corresponds to an
177 /** @name Enable Set Register
178 * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
179 * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
181 * There are registers for each of the CPU interfaces at offset 0x100. With up
182 * to 8 registers aliased to the same address. A register set for the SPI
183 * interrupts is available to all CPU interfaces.
184 * There are up to 32 of these registers staring at location 0x104.
187 #define XSCUGIC_INT_EN_MASK 0x00000001 /**< Each bit corresponds to an
191 /** @name Enable Clear Register
192 * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
193 * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
194 * sets the corresponding bit to 0.
195 * There are registers for each of the CPU interfaces at offset 0x180. With up
196 * to 8 registers aliased to the same address.
197 * A register set for the SPI interrupts is available to all CPU interfaces.
198 * There are up to 32 of these registers staring at location 0x184.
201 #define XSCUGIC_INT_CLR_MASK 0x00000001 /**< Each bit corresponds to an
205 /** @name Pending Set Register
206 * Each bit controls the Pending or Active and Pending state of an interrupt, a
207 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
208 * an interrupt to the pending state.
209 * There are registers for each of the CPU interfaces at offset 0x200. With up
210 * to 8 registers aliased to the same address.
211 * A register set for the SPI interrupts is available to all CPU interfaces.
212 * There are up to 32 of these registers staring at location 0x204.
215 #define XSCUGIC_PEND_SET_MASK 0x00000001 /**< Each bit corresponds to an
219 /** @name Pending Clear Register
220 * Each bit can clear the Pending or Active and Pending state of an interrupt, a
221 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
222 * clears the pending state of an interrupt.
223 * There are registers for each of the CPU interfaces at offset 0x280. With up
224 * to 8 registers aliased to the same address.
225 * A register set for the SPI interrupts is available to all CPU interfaces.
226 * There are up to 32 of these registers staring at location 0x284.
229 #define XSCUGIC_PEND_CLR_MASK 0x00000001 /**< Each bit corresponds to an
233 /** @name Active Status Register
234 * Each bit provides the Active status of an interrupt, a
235 * 0 is not Active, a 1 is Active. This is a read only register.
236 * There are registers for each of the CPU interfaces at offset 0x300. With up
237 * to 8 registers aliased to each address.
238 * A register set for the SPI interrupts is available to all CPU interfaces.
239 * There are up to 32 of these registers staring at location 0x380.
242 #define XSCUGIC_ACTIVE_MASK 0x00000001 /**< Each bit corresponds to an
246 /** @name Priority Level Register
247 * Each byte in a Priority Level Register sets the priority level of an
248 * interrupt. Reading the register provides the priority level of an interrupt.
249 * There are registers for each of the CPU interfaces at offset 0x400 through
250 * 0x41C. With up to 8 registers aliased to each address.
251 * 0 is highest priority, 0xFF is lowest.
252 * A register set for the SPI interrupts is available to all CPU interfaces.
253 * There are up to 255 of these registers staring at location 0x420.
256 #define XSCUGIC_PRIORITY_MASK 0x000000FF /**< Each Byte corresponds to an
258 #define XSCUGIC_PRIORITY_MAX 0x000000FF /**< Highest value of a priority
259 actually the lowest priority*/
262 /** @name SPI Target Register 0x800-0x8FB
263 * Each byte references a separate SPI and programs which of the up to 8 CPU
264 * interfaces are sent a Pending interrupt.
265 * There are registers for each of the CPU interfaces at offset 0x800 through
266 * 0x81C. With up to 8 registers aliased to each address.
267 * A register set for the SPI interrupts is available to all CPU interfaces.
268 * There are up to 255 of these registers staring at location 0x820.
270 * This driver does not support multiple CPU interfaces. These are included
271 * for complete documentation.
274 #define XSCUGIC_SPI_CPU7_MASK 0x00000080 /**< CPU 7 Mask*/
275 #define XSCUGIC_SPI_CPU6_MASK 0x00000040 /**< CPU 6 Mask*/
276 #define XSCUGIC_SPI_CPU5_MASK 0x00000020 /**< CPU 5 Mask*/
277 #define XSCUGIC_SPI_CPU4_MASK 0x00000010 /**< CPU 4 Mask*/
278 #define XSCUGIC_SPI_CPU3_MASK 0x00000008 /**< CPU 3 Mask*/
279 #define XSCUGIC_SPI_CPU2_MASK 0x00000003 /**< CPU 2 Mask*/
280 #define XSCUGIC_SPI_CPU1_MASK 0x00000002 /**< CPU 1 Mask*/
281 #define XSCUGIC_SPI_CPU0_MASK 0x00000001 /**< CPU 0 Mask*/
284 /** @name Interrupt Configuration Register 0xC00-0xCFC
285 * The interrupt configuration registers program an SFI to be active HIGH level
286 * sensitive or rising edge sensitive.
287 * Each bit pair describes the configuration for an INT_ID.
288 * SFI Read Only b10 always
289 * PPI Read Only depending on how the PPIs are configured.
290 * b01 Active HIGH level sensitive
291 * b11 Rising edge sensitive
292 * SPI LSB is read only.
293 * b01 Active HIGH level sensitive
294 * b11 Rising edge sensitive/
295 * There are registers for each of the CPU interfaces at offset 0xC00 through
296 * 0xC04. With up to 8 registers aliased to each address.
297 * A register set for the SPI interrupts is available to all CPU interfaces.
298 * There are up to 255 of these registers staring at location 0xC08.
301 #define XSCUGIC_INT_CFG_MASK 0x00000003 /**< */
304 /** @name PPI Status Register
305 * Enables an external AMBA master to access the status of the PPI inputs.
306 * A CPU can only read the status of its local PPI signals and cannot read the
307 * status for other CPUs.
308 * This register is aliased for each CPU interface.
311 #define XSCUGIC_PPI_C15_MASK 0x00008000 /**< PPI Status */
312 #define XSCUGIC_PPI_C14_MASK 0x00004000 /**< PPI Status */
313 #define XSCUGIC_PPI_C13_MASK 0x00002000 /**< PPI Status */
314 #define XSCUGIC_PPI_C12_MASK 0x00001000 /**< PPI Status */
315 #define XSCUGIC_PPI_C11_MASK 0x00000800 /**< PPI Status */
316 #define XSCUGIC_PPI_C10_MASK 0x00000400 /**< PPI Status */
317 #define XSCUGIC_PPI_C09_MASK 0x00000200 /**< PPI Status */
318 #define XSCUGIC_PPI_C08_MASK 0x00000100 /**< PPI Status */
319 #define XSCUGIC_PPI_C07_MASK 0x00000080 /**< PPI Status */
320 #define XSCUGIC_PPI_C06_MASK 0x00000040 /**< PPI Status */
321 #define XSCUGIC_PPI_C05_MASK 0x00000020 /**< PPI Status */
322 #define XSCUGIC_PPI_C04_MASK 0x00000010 /**< PPI Status */
323 #define XSCUGIC_PPI_C03_MASK 0x00000008 /**< PPI Status */
324 #define XSCUGIC_PPI_C02_MASK 0x00000004 /**< PPI Status */
325 #define XSCUGIC_PPI_C01_MASK 0x00000002 /**< PPI Status */
326 #define XSCUGIC_PPI_C00_MASK 0x00000001 /**< PPI Status */
329 /** @name SPI Status Register 0xd04-0xd7C
330 * Enables an external AMBA master to access the status of the SPI inputs.
331 * There are up to 63 registers if the maximum number of SPI inputs are
335 #define XSCUGIC_SPI_N_MASK 0x00000001 /**< Each bit corresponds to an SPI
339 /** @name AHB Configuration Register
340 * Provides the status of the CFGBIGEND input signal and allows the endianess
341 * of the GIC to be set.
344 #define XSCUGIC_AHB_END_MASK 0x00000004 /**< 0-GIC uses little Endian,
345 1-GIC uses Big Endian */
346 #define XSCUGIC_AHB_ENDOVR_MASK 0x00000002 /**< 0-Uses CFGBIGEND control,
347 1-use the AHB_END bit */
348 #define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001 /**< State of CFGBIGEND */
352 /** @name Software Triggered Interrupt Register
353 * Controls issueing of software interrupts.
356 #define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000
357 #define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000 /**< Target List filter
358 b00-Use the target List
359 b01-All CPUs except requester
362 #define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000 /**< CPU Target list */
363 #define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000 /**< 0= Use a secure interrupt */
364 #define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000F /**< Set to the INTID
365 signaled to the CPU*/
368 /** @name CPU Interface Register Map
370 * Define the offsets from the base address for all CPU registers of the
371 * interrupt controller, some registers may be reserved in the hardware device.
374 #define XSCUGIC_CONTROL_OFFSET 0x00000000 /**< CPU Interface Control
376 #define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004 /**< Priority Mask Reg */
377 #define XSCUGIC_BIN_PT_OFFSET 0x00000008 /**< Binary Point Register */
378 #define XSCUGIC_INT_ACK_OFFSET 0x0000000C /**< Interrupt ACK Reg */
379 #define XSCUGIC_EOI_OFFSET 0x00000010 /**< End of Interrupt Reg */
380 #define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014 /**< Running Priority Reg */
381 #define XSCUGIC_HI_PEND_OFFSET 0x00000018 /**< Highest Pending Interrupt
383 #define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001C /**< Aliased non-Secure
384 Binary Point Register */
386 /**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
391 /** @name Control Register
392 * CPU Interface Control register definitions
393 * All bits are defined here although some are not available in the non-secure
397 #define XSCUGIC_CNTR_SBPR_MASK 0x00000010 /**< Secure Binary Pointer,
398 0=separate registers,
399 1=both use bin_pt_s */
400 #define XSCUGIC_CNTR_FIQEN_MASK 0x00000008 /**< Use nFIQ_C for secure
403 1=Use FIQ for secure, IRQ for non*/
404 #define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004 /**< Ack control for secure or non secure */
405 #define XSCUGIC_CNTR_EN_NS_MASK 0x00000002 /**< Non Secure enable */
406 #define XSCUGIC_CNTR_EN_S_MASK 0x00000001 /**< Secure enable, 0=Disabled, 1=Enabled */
409 /** @name Priority Mask Register
410 * Priority Mask register definitions
411 * The CPU interface does not send interrupt if the level of the interrupt is
412 * lower than the level of the register.
415 #define XSCUGIC_PRIORITY_MASK 0x000000FF /**< All interrupts */
418 /** @name Binary Point Register
419 * Binary Point register definitions
423 #define XSCUGIC_BIN_PT_MASK 0x00000007 /**< Binary point mask value
424 Value Secure Non-secure
436 /** @name Interrupt Acknowledge Register
437 * Interrupt Acknowledge register definitions
438 * Identifies the current Pending interrupt, and the CPU ID for software
441 #define XSCUGIC_ACK_INTID_MASK 0x000003FF /**< Interrupt ID */
442 #define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */
445 /** @name End of Interrupt Register
446 * End of Interrupt register definitions
447 * Allows the CPU to signal the GIC when it completes an interrupt service
450 #define XSCUGIC_EOI_INTID_MASK 0x000003FF /**< Interrupt ID */
454 /** @name Running Priority Register
455 * Running Priority register definitions
456 * Identifies the interrupt priority level of the highest priority active
459 #define XSCUGIC_RUN_PRIORITY_MASK 0x00000FF /**< Interrupt Priority */
463 * Highest Pending Interrupt register definitions
464 * Identifies the interrupt priority of the highest priority pending interupt
466 #define XSCUGIC_PEND_INTID_MASK 0x000003FF /**< Pending Interrupt ID */
467 #define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */
470 /***************** Macros (Inline Functions) Definitions *********************/
472 /****************************************************************************/
475 * Read the Interrupt Configuration Register offset for an interrupt id.
477 * @param InterruptID is the interrupt number.
479 * @return The 32-bit value of the offset
483 *****************************************************************************/
484 #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
485 (XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4))
487 /****************************************************************************/
490 * Read the Interrupt Priority Register offset for an interrupt id.
492 * @param InterruptID is the interrupt number.
494 * @return The 32-bit value of the offset
498 *****************************************************************************/
499 #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
500 (XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4))
502 /****************************************************************************/
505 * Read the SPI Target Register offset for an interrupt id.
507 * @param InterruptID is the interrupt number.
509 * @return The 32-bit value of the offset
513 *****************************************************************************/
514 #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
515 (XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4))
517 /****************************************************************************/
520 * Read the Interrupt Clear-Enable Register offset for an interrupt ID
522 * @param Register is the register offset for the clear/enable bank.
523 * @param InterruptID is the interrupt number.
525 * @return The 32-bit value of the offset
529 *****************************************************************************/
530 #define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \
531 (Register + ((InterruptID/32) * 4))
533 /****************************************************************************/
536 * Read the given Intc register.
538 * @param BaseAddress is the base address of the device.
539 * @param RegOffset is the register offset to be read
541 * @return The 32-bit value of the register
545 * u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
547 *****************************************************************************/
548 #define XScuGic_ReadReg(BaseAddress, RegOffset) \
549 (Xil_In32((BaseAddress) + (RegOffset)))
552 /****************************************************************************/
555 * Write the given Intc register.
557 * @param BaseAddress is the base address of the device.
558 * @param RegOffset is the register offset to be written
559 * @param Data is the 32-bit value to write to the register
565 * void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
567 *****************************************************************************/
568 #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
569 (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data)))
572 /****************************************************************************/
575 * Enable specific interrupt(s) in the interrupt controller.
577 * @param DistBaseAddress is the Distributor Register base address of the
579 * @param Int_Id is the ID of the interrupt source and should be in the
580 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
584 * @note C-style signature:
585 * void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id);
587 *****************************************************************************/
588 #define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
589 XScuGic_WriteReg((DistBaseAddress), \
590 XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \
591 (1 << (Int_Id % 32)))
593 /****************************************************************************/
596 * Disable specific interrupt(s) in the interrupt controller.
598 * @param DistBaseAddress is the Distributor Register base address of the
600 * @param Int_Id is the ID of the interrupt source and should be in the
601 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
606 * @note C-style signature:
607 * void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id);
609 *****************************************************************************/
610 #define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
611 XScuGic_WriteReg((DistBaseAddress), \
612 XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \
613 (1 << (Int_Id % 32)))
616 /************************** Function Prototypes ******************************/
618 void XScuGic_DeviceInterruptHandler(void *DeviceId);
619 int XScuGic_DeviceInitialize(u32 DeviceId);
620 void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId,
621 Xil_InterruptHandler Handler, void *CallBackRef);
622 void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
623 u8 Priority, u8 Trigger);
624 void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
625 u8 *Priority, u8 *Trigger);
626 /************************** Variable Definitions *****************************/
631 #endif /* end of protection macro */