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31 ******************************************************************************/
32 /****************************************************************************/
37 * This file contains the hardware interface to the Xilinx SCU private Watch Dog
41 * MODIFICATION HISTORY:
43 * Ver Who Date Changes
44 * ----- --- -------- ---------------------------------------------
45 * 1.00a sdm 01/15/10 First release
46 * 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
47 * of 0x20 as the base address obtained from the tools
49 * 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
50 * when the xstatus.h in the common driver overwrites
51 * the xstatus.h of the standalone BSP during the
55 ******************************************************************************/
56 #ifndef XSCUWDT_HW_H /* prevent circular inclusions */
57 #define XSCUWDT_HW_H /* by using protection macros */
63 /***************************** Include Files *********************************/
65 #include "xil_types.h"
67 #include "xil_assert.h"
68 /************************** Constant Definitions *****************************/
70 /** @name Register Map
71 * Offsets of registers from the start of the device. The WDT registers start at
76 #define XSCUWDT_LOAD_OFFSET 0x00 /**< Watchdog Load Register */
77 #define XSCUWDT_COUNTER_OFFSET 0x04 /**< Watchdog Counter Register */
78 #define XSCUWDT_CONTROL_OFFSET 0x08 /**< Watchdog Control Register */
79 #define XSCUWDT_ISR_OFFSET 0x0C /**< Watchdog Interrupt Status Register */
80 #define XSCUWDT_RST_STS_OFFSET 0x10 /**< Watchdog Reset Status Register */
81 #define XSCUWDT_DISABLE_OFFSET 0x14 /**< Watchdog Disable Register */
84 /** @name Watchdog Control register
85 * This register bits control the prescaler, WD/Timer mode, Intr enable,
86 * auto-reload, watchdog enable.
90 #define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */
91 #define XSCUWDT_CONTROL_PRESCALER_SHIFT 8
92 #define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008 /**< Watchdog/Timer mode */
93 #define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004 /**< Intr enable (in
95 #define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in
97 #define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001 /**< Watchdog enable */
100 /** @name Interrupt Status register
101 * This register indicates the Counter register has reached zero in Counter
106 #define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */
109 /** @name Reset Status register
110 * This register indicates the Counter register has reached zero in Watchdog
111 * mode and a reset request is sent.
115 #define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001 /**< Time out occured */
118 /** @name Disable register
119 * This register is used to switch from watchdog mode to timer mode.
120 * The software must write 0x12345678 and 0x87654321 successively to the
121 * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
122 * Control Register is set to zero.
125 #define XSCUWDT_DISABLE_VALUE1 0x12345678 /**< Watchdog mode disable
127 #define XSCUWDT_DISABLE_VALUE2 0x87654321 /**< Watchdog mode disable
131 /**************************** Type Definitions *******************************/
133 /***************** Macros (Inline Functions) Definitions *********************/
135 /****************************************************************************/
138 * Read the given register.
140 * @param BaseAddr is the base address of the device
141 * @param RegOffset is the register offset to be read
143 * @return The 32-bit value of the register
145 * @note C-style signature:
146 * u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
148 *****************************************************************************/
149 #define XScuWdt_ReadReg(BaseAddr, RegOffset) \
150 Xil_In32((BaseAddr) + (RegOffset))
152 /****************************************************************************/
155 * Write the given register.
157 * @param BaseAddr is the base address of the device
158 * @param RegOffset is the register offset to be written
159 * @param Data is the 32-bit value to write to the register
163 * @note C-style signature:
164 * void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
166 *****************************************************************************/
167 #define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
168 Xil_Out32((BaseAddr) + (RegOffset), (Data))
170 /************************** Function Prototypes ******************************/
172 /************************** Variable Definitions *****************************/
178 #endif /* end of protection macro */