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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This file defines the hardware interface to one of the three timer counters
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ------ -------- -------------------------------------------------
46 * 1.00a drg/jz 01/21/10 First release
50 ******************************************************************************/
52 #ifndef XTTCPS_HW_H /* prevent circular inclusions */
53 #define XTTCPS_HW_H /* by using protection macros */
59 /***************************** Include Files *********************************/
61 #include "xil_types.h"
62 #include "xil_assert.h"
65 /************************** Constant Definitions *****************************/
67 /** @name Register Map
69 * Register offsets from the base address of the device.
73 #define XTTCPS_CLK_CNTRL_OFFSET 0x00000000 /**< Clock Control Register */
74 #define XTTCPS_CNT_CNTRL_OFFSET 0x0000000C /**< Counter Control Register*/
75 #define XTTCPS_COUNT_VALUE_OFFSET 0x00000018 /**< Current Counter Value */
76 #define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024 /**< Interval Count Value */
77 #define XTTCPS_MATCH_0_OFFSET 0x00000030 /**< Match 1 value */
78 #define XTTCPS_MATCH_1_OFFSET 0x0000003C /**< Match 2 value */
79 #define XTTCPS_MATCH_2_OFFSET 0x00000048 /**< Match 3 value */
80 #define XTTCPS_ISR_OFFSET 0x00000054 /**< Interrupt Status Register */
81 #define XTTCPS_IER_OFFSET 0x00000060 /**< Interrupt Enable Register */
84 /** @name Clock Control Register
85 * Clock Control Register definitions
88 #define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */
89 #define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */
90 #define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */
91 #define XTTCPS_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */
92 #define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */
93 #define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */
96 /** @name Counter Control Register
97 * Counter Control Register definitions
100 #define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */
101 #define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002 /**< Interval mode */
102 #define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */
103 #define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */
104 #define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */
105 #define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */
106 #define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */
107 #define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */
110 /** @name Current Counter Value Register
111 * Current Counter Value Register definitions
114 #define XTTCPS_COUNT_VALUE_MASK 0x0000FFFF /**< 16-bit counter value */
117 /** @name Interval Value Register
118 * Interval Value Register is the maximum value the counter will count up or
122 #define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFF /**< 16-bit Interval value*/
125 /** @name Match Registers
126 * Definitions for Match registers, each timer counter has three match
130 #define XTTCPS_MATCH_MASK 0x0000FFFF /**< 16-bit Match value */
131 #define XTTCPS_NUM_MATCH_REG 3 /**< Num of Match reg */
134 /** @name Interrupt Registers
135 * Following register bit mask is for all interrupt registers.
139 #define XTTCPS_IXR_INTERVAL_MASK 0x00000001 /**< Interval Interrupt */
140 #define XTTCPS_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */
141 #define XTTCPS_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */
142 #define XTTCPS_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */
143 #define XTTCPS_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */
144 #define XTTCPS_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */
148 /***************** Macros (Inline Functions) Definitions *********************/
150 /****************************************************************************/
153 * Read the given Timer Counter register.
155 * @param BaseAddress is the base address of the timer counter device.
156 * @param RegOffset is the register offset to be read
158 * @return The 32-bit value of the register
160 * @note C-style signature:
161 * u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
163 *****************************************************************************/
164 #define XTtcPs_ReadReg(BaseAddress, RegOffset) \
165 (Xil_In32((BaseAddress) + (RegOffset)))
167 /****************************************************************************/
170 * Write the given Timer Counter register.
172 * @param BaseAddress is the base address of the timer counter device.
173 * @param RegOffset is the register offset to be written
174 * @param Data is the 32-bit value to write to the register
178 * @note C-style signature:
179 * void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
182 *****************************************************************************/
183 #define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
184 (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
186 /****************************************************************************/
189 * Calculate a match register offset using the Match Register index.
191 * @param MatchIndex is the 0-2 value of the match register
193 * @return MATCH_N_OFFSET.
195 * @note C-style signature:
196 * u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
198 *****************************************************************************/
199 #define XTtcPs_Match_N_Offset(MatchIndex) \
200 (XTTCPS_MATCH_0_OFFSET + (12 * (MatchIndex)))
202 /************************** Function Prototypes ******************************/
204 /************************** Variable Definitions *****************************/
208 #endif /* end of protection macro */