1 /******************************************************************************
3 * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup canps_v2_0
39 * This header file contains the identifiers and basic driver functions (or
40 * macros) that can be used to access the device. Other driver functions
41 * are defined in xcanps.h.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ----- -------- -----------------------------------------------
48 * 1.00a xd/sv 01/12/10 First release
49 * 1.01a sbs 12/27/11 Updated the Register/bit definitions
50 * Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
51 * Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
52 * Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
53 * Changed XCANPS_IXR_RXFLL_MASK to
54 * XCANPS_IXR_RXFWMFLL_MASK
56 * XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
57 * XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
58 * XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
59 * XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
60 * 1.02a adk 08/08/13 Updated for inclding the function prototype
63 ******************************************************************************/
65 #ifndef XCANPS_HW_H /* prevent circular inclusions */
66 #define XCANPS_HW_H /* by using protection macros */
73 /***************************** Include Files *********************************/
75 #include "xil_types.h"
76 #include "xil_assert.h"
79 /************************** Constant Definitions *****************************/
81 /** @name Register offsets for the CAN. Each register is 32 bits.
84 #define XCANPS_SRR_OFFSET 0x00 /**< Software Reset Register */
85 #define XCANPS_MSR_OFFSET 0x04 /**< Mode Select Register */
86 #define XCANPS_BRPR_OFFSET 0x08 /**< Baud Rate Prescaler */
87 #define XCANPS_BTR_OFFSET 0x0C /**< Bit Timing Register */
88 #define XCANPS_ECR_OFFSET 0x10 /**< Error Counter Register */
89 #define XCANPS_ESR_OFFSET 0x14 /**< Error Status Register */
90 #define XCANPS_SR_OFFSET 0x18 /**< Status Register */
92 #define XCANPS_ISR_OFFSET 0x1C /**< Interrupt Status Register */
93 #define XCANPS_IER_OFFSET 0x20 /**< Interrupt Enable Register */
94 #define XCANPS_ICR_OFFSET 0x24 /**< Interrupt Clear Register */
95 #define XCANPS_TCR_OFFSET 0x28 /**< Timestamp Control Register */
96 #define XCANPS_WIR_OFFSET 0x2C /**< Watermark Interrupt Reg */
98 #define XCANPS_TXFIFO_ID_OFFSET 0x30 /**< TX FIFO ID */
99 #define XCANPS_TXFIFO_DLC_OFFSET 0x34 /**< TX FIFO DLC */
100 #define XCANPS_TXFIFO_DW1_OFFSET 0x38 /**< TX FIFO Data Word 1 */
101 #define XCANPS_TXFIFO_DW2_OFFSET 0x3C /**< TX FIFO Data Word 2 */
103 #define XCANPS_TXHPB_ID_OFFSET 0x40 /**< TX High Priority Buffer ID */
104 #define XCANPS_TXHPB_DLC_OFFSET 0x44 /**< TX High Priority Buffer DLC */
105 #define XCANPS_TXHPB_DW1_OFFSET 0x48 /**< TX High Priority Buf Data 1 */
106 #define XCANPS_TXHPB_DW2_OFFSET 0x4C /**< TX High Priority Buf Data Word 2 */
108 #define XCANPS_RXFIFO_ID_OFFSET 0x50 /**< RX FIFO ID */
109 #define XCANPS_RXFIFO_DLC_OFFSET 0x54 /**< RX FIFO DLC */
110 #define XCANPS_RXFIFO_DW1_OFFSET 0x58 /**< RX FIFO Data Word 1 */
111 #define XCANPS_RXFIFO_DW2_OFFSET 0x5C /**< RX FIFO Data Word 2 */
113 #define XCANPS_AFR_OFFSET 0x60 /**< Acceptance Filter Register */
114 #define XCANPS_AFMR1_OFFSET 0x64 /**< Acceptance Filter Mask 1 */
115 #define XCANPS_AFIR1_OFFSET 0x68 /**< Acceptance Filter ID 1 */
116 #define XCANPS_AFMR2_OFFSET 0x6C /**< Acceptance Filter Mask 2 */
117 #define XCANPS_AFIR2_OFFSET 0x70 /**< Acceptance Filter ID 2 */
118 #define XCANPS_AFMR3_OFFSET 0x74 /**< Acceptance Filter Mask 3 */
119 #define XCANPS_AFIR3_OFFSET 0x78 /**< Acceptance Filter ID 3 */
120 #define XCANPS_AFMR4_OFFSET 0x7C /**< Acceptance Filter Mask 4 */
121 #define XCANPS_AFIR4_OFFSET 0x80 /**< Acceptance Filter ID 4 */
124 /** @name Software Reset Register (SRR) Bit Definitions and Masks
127 #define XCANPS_SRR_CEN_MASK 0x00000002 /**< Can Enable */
128 #define XCANPS_SRR_SRST_MASK 0x00000001 /**< Reset */
131 /** @name Mode Select Register (MSR) Bit Definitions and Masks
134 #define XCANPS_MSR_SNOOP_MASK 0x00000004 /**< Snoop Mode Select */
135 #define XCANPS_MSR_LBACK_MASK 0x00000002 /**< Loop Back Mode Select */
136 #define XCANPS_MSR_SLEEP_MASK 0x00000001 /**< Sleep Mode Select */
139 /** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks
142 #define XCANPS_BRPR_BRP_MASK 0x000000FF /**< Baud Rate Prescaler */
145 /** @name Bit Timing Register (BTR) Bit Definitions and Masks
148 #define XCANPS_BTR_SJW_MASK 0x00000180 /**< Synchronization Jump Width */
149 #define XCANPS_BTR_SJW_SHIFT 7
150 #define XCANPS_BTR_TS2_MASK 0x00000070 /**< Time Segment 2 */
151 #define XCANPS_BTR_TS2_SHIFT 4
152 #define XCANPS_BTR_TS1_MASK 0x0000000F /**< Time Segment 1 */
155 /** @name Error Counter Register (ECR) Bit Definitions and Masks
158 #define XCANPS_ECR_REC_MASK 0x0000FF00 /**< Receive Error Counter */
159 #define XCANPS_ECR_REC_SHIFT 8
160 #define XCANPS_ECR_TEC_MASK 0x000000FF /**< Transmit Error Counter */
163 /** @name Error Status Register (ESR) Bit Definitions and Masks
166 #define XCANPS_ESR_ACKER_MASK 0x00000010 /**< ACK Error */
167 #define XCANPS_ESR_BERR_MASK 0x00000008 /**< Bit Error */
168 #define XCANPS_ESR_STER_MASK 0x00000004 /**< Stuff Error */
169 #define XCANPS_ESR_FMER_MASK 0x00000002 /**< Form Error */
170 #define XCANPS_ESR_CRCER_MASK 0x00000001 /**< CRC Error */
173 /** @name Status Register (SR) Bit Definitions and Masks
176 #define XCANPS_SR_SNOOP_MASK 0x00001000 /**< Snoop Mask */
177 #define XCANPS_SR_ACFBSY_MASK 0x00000800 /**< Acceptance Filter busy */
178 #define XCANPS_SR_TXFLL_MASK 0x00000400 /**< TX FIFO is full */
179 #define XCANPS_SR_TXBFLL_MASK 0x00000200 /**< TX High Priority Buffer full */
180 #define XCANPS_SR_ESTAT_MASK 0x00000180 /**< Error Status */
181 #define XCANPS_SR_ESTAT_SHIFT 7
182 #define XCANPS_SR_ERRWRN_MASK 0x00000040 /**< Error Warning */
183 #define XCANPS_SR_BBSY_MASK 0x00000020 /**< Bus Busy */
184 #define XCANPS_SR_BIDLE_MASK 0x00000010 /**< Bus Idle */
185 #define XCANPS_SR_NORMAL_MASK 0x00000008 /**< Normal Mode */
186 #define XCANPS_SR_SLEEP_MASK 0x00000004 /**< Sleep Mode */
187 #define XCANPS_SR_LBACK_MASK 0x00000002 /**< Loop Back Mode */
188 #define XCANPS_SR_CONFIG_MASK 0x00000001 /**< Configuration Mode */
191 /** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks
194 #define XCANPS_IXR_TXFEMP_MASK 0x00004000 /**< Tx Fifo Empty Interrupt */
195 #define XCANPS_IXR_TXFWMEMP_MASK 0x00002000 /**< Tx Fifo Watermark Empty */
196 #define XCANPS_IXR_RXFWMFLL_MASK 0x00001000 /**< Rx FIFO Watermark Full */
197 #define XCANPS_IXR_WKUP_MASK 0x00000800 /**< Wake up Interrupt */
198 #define XCANPS_IXR_SLP_MASK 0x00000400 /**< Sleep Interrupt */
199 #define XCANPS_IXR_BSOFF_MASK 0x00000200 /**< Bus Off Interrupt */
200 #define XCANPS_IXR_ERROR_MASK 0x00000100 /**< Error Interrupt */
201 #define XCANPS_IXR_RXNEMP_MASK 0x00000080 /**< RX FIFO Not Empty Interrupt */
202 #define XCANPS_IXR_RXOFLW_MASK 0x00000040 /**< RX FIFO Overflow Interrupt */
203 #define XCANPS_IXR_RXUFLW_MASK 0x00000020 /**< RX FIFO Underflow Interrupt */
204 #define XCANPS_IXR_RXOK_MASK 0x00000010 /**< New Message Received Intr */
205 #define XCANPS_IXR_TXBFLL_MASK 0x00000008 /**< TX High Priority Buf Full */
206 #define XCANPS_IXR_TXFLL_MASK 0x00000004 /**< TX FIFO Full Interrupt */
207 #define XCANPS_IXR_TXOK_MASK 0x00000002 /**< TX Successful Interrupt */
208 #define XCANPS_IXR_ARBLST_MASK 0x00000001 /**< Arbitration Lost Interrupt */
209 #define XCANPS_IXR_ALL (XCANPS_IXR_RXFWMFLL_MASK | \
210 XCANPS_IXR_WKUP_MASK | \
211 XCANPS_IXR_SLP_MASK | \
212 XCANPS_IXR_BSOFF_MASK | \
213 XCANPS_IXR_ERROR_MASK | \
214 XCANPS_IXR_RXNEMP_MASK | \
215 XCANPS_IXR_RXOFLW_MASK | \
216 XCANPS_IXR_RXUFLW_MASK | \
217 XCANPS_IXR_RXOK_MASK | \
218 XCANPS_IXR_TXBFLL_MASK | \
219 XCANPS_IXR_TXFLL_MASK | \
220 XCANPS_IXR_TXOK_MASK | \
221 XCANPS_IXR_ARBLST_MASK)
224 /** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks
227 #define XCANPS_TCR_CTS_MASK 0x00000001 /**< Clear Timestamp counter mask */
230 /** @name CAN Watermark Register (WIR) Bit Definitions and Masks
233 #define XCANPS_WIR_FW_MASK 0x0000003F /**< Rx Full Threshold mask */
234 #define XCANPS_WIR_EW_MASK 0x00003F00 /**< Tx Empty Threshold mask */
235 #define XCANPS_WIR_EW_SHIFT 0x00000008 /**< Tx Empty Threshold shift */
239 /** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter
240 Mask/Acceptance Filter ID)
243 #define XCANPS_IDR_ID1_MASK 0xFFE00000 /**< Standard Messg Identifier */
244 #define XCANPS_IDR_ID1_SHIFT 21
245 #define XCANPS_IDR_SRR_MASK 0x00100000 /**< Substitute Remote TX Req */
246 #define XCANPS_IDR_SRR_SHIFT 20
247 #define XCANPS_IDR_IDE_MASK 0x00080000 /**< Identifier Extension */
248 #define XCANPS_IDR_IDE_SHIFT 19
249 #define XCANPS_IDR_ID2_MASK 0x0007FFFE /**< Extended Message Ident */
250 #define XCANPS_IDR_ID2_SHIFT 1
251 #define XCANPS_IDR_RTR_MASK 0x00000001 /**< Remote TX Request */
254 /** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX)
257 #define XCANPS_DLCR_DLC_MASK 0xF0000000 /**< Data Length Code */
258 #define XCANPS_DLCR_DLC_SHIFT 28
259 #define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFF /**< Timestamp Mask (Rx only) */
263 /** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX)
266 #define XCANPS_DW1R_DB0_MASK 0xFF000000 /**< Data Byte 0 */
267 #define XCANPS_DW1R_DB0_SHIFT 24
268 #define XCANPS_DW1R_DB1_MASK 0x00FF0000 /**< Data Byte 1 */
269 #define XCANPS_DW1R_DB1_SHIFT 16
270 #define XCANPS_DW1R_DB2_MASK 0x0000FF00 /**< Data Byte 2 */
271 #define XCANPS_DW1R_DB2_SHIFT 8
272 #define XCANPS_DW1R_DB3_MASK 0x000000FF /**< Data Byte 3 */
275 /** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX)
278 #define XCANPS_DW2R_DB4_MASK 0xFF000000 /**< Data Byte 4 */
279 #define XCANPS_DW2R_DB4_SHIFT 24
280 #define XCANPS_DW2R_DB5_MASK 0x00FF0000 /**< Data Byte 5 */
281 #define XCANPS_DW2R_DB5_SHIFT 16
282 #define XCANPS_DW2R_DB6_MASK 0x0000FF00 /**< Data Byte 6 */
283 #define XCANPS_DW2R_DB6_SHIFT 8
284 #define XCANPS_DW2R_DB7_MASK 0x000000FF /**< Data Byte 7 */
287 /** @name Acceptance Filter Register (AFR) Bit Definitions and Masks
290 #define XCANPS_AFR_UAF4_MASK 0x00000008 /**< Use Acceptance Filter No.4 */
291 #define XCANPS_AFR_UAF3_MASK 0x00000004 /**< Use Acceptance Filter No.3 */
292 #define XCANPS_AFR_UAF2_MASK 0x00000002 /**< Use Acceptance Filter No.2 */
293 #define XCANPS_AFR_UAF1_MASK 0x00000001 /**< Use Acceptance Filter No.1 */
294 #define XCANPS_AFR_UAF_ALL_MASK (XCANPS_AFR_UAF4_MASK | \
295 XCANPS_AFR_UAF3_MASK | \
296 XCANPS_AFR_UAF2_MASK | \
297 XCANPS_AFR_UAF1_MASK)
300 /** @name CAN frame length constants
303 #define XCANPS_MAX_FRAME_SIZE 16 /**< Maximum CAN frame length in bytes */
306 /* For backwards compatibilty */
307 #define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET
308 #define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET
309 #define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET
310 #define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET
312 #define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK
313 #define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET
314 #define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK
319 /**************************** Type Definitions *******************************/
321 /***************** Macros (Inline Functions) Definitions *********************/
323 /****************************************************************************/
326 * This macro reads the given register.
328 * @param BaseAddr is the base address of the device.
329 * @param RegOffset is the register offset to be read.
331 * @return The 32-bit value of the register
335 *****************************************************************************/
336 #define XCanPs_ReadReg(BaseAddr, RegOffset) \
337 Xil_In32((BaseAddr) + (RegOffset))
340 /****************************************************************************/
343 * This macro writes the given register.
345 * @param BaseAddr is the base address of the device.
346 * @param RegOffset is the register offset to be written.
347 * @param Data is the 32-bit value to write to the register.
353 *****************************************************************************/
354 #define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \
355 Xil_Out32((BaseAddr) + (RegOffset), (Data))
357 /************************** Function Prototypes ******************************/
359 * Perform reset operation to the CanPs interface
361 void XCanPs_ResetHw(u32 BaseAddr);
367 #endif /* end of protection macro */