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   1 /******************************************************************************
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  13 * all copies or substantial portions of the Software.
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  18 *
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  32 /****************************************************************************/
  33 /**
  34 *
  35 * @file xdevcfg_hw.h
  36 * @addtogroup devcfg_v3_3
  37 * @{
  38 *
  39 * This file contains the hardware interface to the Device Config Interface.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who Date     Changes
  45 * ----- --- -------- ---------------------------------------------
  46 * 1.00a hvm 02/07/11 First release
  47 * 2.01a nm  08/01/12 Added defines for the PS Version bits,
  48 *                    removed the FIFO Flush bits from the
  49 *                    Miscellaneous Control Reg
  50 * 2.03a nm  04/19/13 Fixed CR# 703728.
  51 *                    Updated the register definitions as per the latest TRM
  52 *                    version UG585 (v1.4) November 16, 2012.
  53 * 2.04a kpc     10/07/13 Added function prototype.
  54 * 3.00a kpc     25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
  55 * </pre>
  56 *
  57 ******************************************************************************/
  58 #ifndef XDCFG_HW_H              /* prevent circular inclusions */
  59 #define XDCFG_HW_H              /* by using protection macros */
  60
  61 #ifdef __cplusplus
  62 extern "C" {
  63 #endif
  64
  65 /***************************** Include Files *********************************/
  66
  67 #include "xil_types.h"
  68 #include "xil_io.h"
  69
  70 /************************** Constant Definitions *****************************/
  71
  72 /** @name Register Map
  73  * Offsets of registers from the start of the device
  74  * @{
  75  */
  76
  77 #define XDCFG_CTRL_OFFSET               0x00 /**< Control Register */
  78 #define XDCFG_LOCK_OFFSET               0x04 /**< Lock Register */
  79 #define XDCFG_CFG_OFFSET                0x08 /**< Configuration Register */
  80 #define XDCFG_INT_STS_OFFSET            0x0C /**< Interrupt Status Register */
  81 #define XDCFG_INT_MASK_OFFSET           0x10 /**< Interrupt Mask Register */
  82 #define XDCFG_STATUS_OFFSET             0x14 /**< Status Register */
  83 #define XDCFG_DMA_SRC_ADDR_OFFSET       0x18 /**< DMA Source Address Register */
  84 #define XDCFG_DMA_DEST_ADDR_OFFSET      0x1C /**< DMA Destination Address Reg */
  85 #define XDCFG_DMA_SRC_LEN_OFFSET        0x20 /**< DMA Source Transfer Length */
  86 #define XDCFG_DMA_DEST_LEN_OFFSET       0x24 /**< DMA Destination Transfer */
  87 #define XDCFG_ROM_SHADOW_OFFSET         0x28 /**< DMA ROM Shadow Register */
  88 #define XDCFG_MULTIBOOT_ADDR_OFFSET     0x2C /**< Multi BootAddress Pointer */
  89 #define XDCFG_SW_ID_OFFSET              0x30 /**< Software ID Register */
  90 #define XDCFG_UNLOCK_OFFSET             0x34 /**< Unlock Register */
  91 #define XDCFG_MCTRL_OFFSET              0x80 /**< Miscellaneous Control Reg */
  92
  93 /* @} */
  94
  95 /** @name Control Register Bit definitions
  96   * @{
  97  */
  98
  99 #define XDCFG_CTRL_FORCE_RST_MASK       0x80000000 /**< Force  into
 100                                                      * Secure Reset
 101                                                      */
 102 #define XDCFG_CTRL_PCFG_PROG_B_MASK     0x40000000 /**< Program signal to
 103                                                      *  Reset FPGA
 104                                                      */
 105 #define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
 106 #define XDCFG_CTRL_PCAP_PR_MASK         0x08000000 /**< Enable PCAP for PR */
 107 #define XDCFG_CTRL_PCAP_MODE_MASK       0x04000000 /**< Enable PCAP */
 108 #define XDCFG_CTRL_PCAP_RATE_EN_MASK    0x02000000 /**< Enable PCAP send data
 109                                                      *  to FPGA every 4 PCAP
 110                                                      *  cycles
 111                                                      */
 112 #define XDCFG_CTRL_MULTIBOOT_EN_MASK    0x01000000 /**< Multiboot Enable */
 113 #define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK  0x00800000 /**< JTAG Chain Disable */
 114 #define XDCFG_CTRL_USER_MODE_MASK       0x00008000 /**< User Mode Mask */
 115 #define XDCFG_CTRL_PCFG_AES_FUSE_MASK   0x00001000 /**< AES key source */
 116 #define XDCFG_CTRL_PCFG_AES_EN_MASK     0x00000E00 /**< AES Enable Mask */
 117 #define XDCFG_CTRL_SEU_EN_MASK          0x00000100 /**< SEU Enable Mask */
 118 #define XDCFG_CTRL_SEC_EN_MASK          0x00000080 /**< Secure/Non Secure
 119                                                      *  Status mask
 120                                                      */
 121 #define XDCFG_CTRL_SPNIDEN_MASK         0x00000040 /**< Secure Non Invasive
 122                                                      *  Debug Enable
 123                                                      */
 124 #define XDCFG_CTRL_SPIDEN_MASK          0x00000020 /**< Secure Invasive
 125                                                      *  Debug Enable
 126                                                      */
 127 #define XDCFG_CTRL_NIDEN_MASK           0x00000010 /**< Non-Invasive Debug
 128                                                      *  Enable
 129                                                      */
 130 #define XDCFG_CTRL_DBGEN_MASK           0x00000008 /**< Invasive Debug
 131                                                      *  Enable
 132                                                      */
 133 #define XDCFG_CTRL_DAP_EN_MASK          0x00000007 /**< DAP Enable Mask */
 134
 135 /* @} */
 136
 137 /** @name Lock register bit definitions
 138   * @{
 139  */
 140
 141 #define XDCFG_LOCK_AES_EFUSE_MASK       0x00000010 /**< Lock AES Efuse bit */
 142 #define XDCFG_LOCK_AES_EN_MASK          0x00000008 /**< Lock AES_EN update */
 143 #define XDCFG_LOCK_SEU_MASK             0x00000004 /**< Lock SEU_En update */
 144 #define XDCFG_LOCK_SEC_MASK             0x00000002 /**< Lock SEC_EN and
 145                                                      *  USER_MODE
 146                                                      */
 147 #define XDCFG_LOCK_DBG_MASK             0x00000001 /**< This bit locks
 148                                                      *  security config
 149                                                      *  including: DAP_En,
 150                                                      *  DBGEN,,
 151                                                      *  NIDEN, SPNIEN
 152                                                      */
 153 /*@}*/
 154
 155
 156
 157 /** @name Config Register Bit definitions
 158   * @{
 159  */
 160 #define XDCFG_CFG_RFIFO_TH_MASK         0x00000C00 /**< Read FIFO
 161                                                      *  Threshold Mask
 162                                                      */
 163 #define XDCFG_CFG_WFIFO_TH_MASK         0x00000300 /**< Write FIFO Threshold
 164                                                      *  Mask
 165                                                      */
 166 #define XDCFG_CFG_RCLK_EDGE_MASK        0x00000080 /**< Read data active
 167                                                      *  clock edge
 168                                                      */
 169 #define XDCFG_CFG_WCLK_EDGE_MASK        0x00000040 /**< Write data active
 170                                                      *  clock edge
 171                                                      */
 172 #define XDCFG_CFG_DISABLE_SRC_INC_MASK  0x00000020 /**< Disable Source address
 173                                                      *  increment mask
 174                                                      */
 175 #define XDCFG_CFG_DISABLE_DST_INC_MASK  0x00000010 /**< Disable Destination
 176                                                      *  address increment
 177                                                      *  mask
 178                                                      */
 179 /* @} */
 180
 181
 182 /** @name Interrupt Status/Mask Register Bit definitions
 183   * @{
 184  */
 185 #define XDCFG_IXR_PSS_GTS_USR_B_MASK    0x80000000 /**< Tri-state IO during
 186                                                      *  HIZ
 187                                                      */
 188 #define XDCFG_IXR_PSS_FST_CFG_B_MASK    0x40000000 /**< First configuration
 189                                                      *  done
 190                                                      */
 191 #define XDCFG_IXR_PSS_GPWRDWN_B_MASK    0x20000000 /**< Global power down */
 192 #define XDCFG_IXR_PSS_GTS_CFG_B_MASK    0x10000000 /**< Tri-state IO during
 193                                                      *  configuration
 194                                                      */
 195 #define XDCFG_IXR_PSS_CFG_RESET_B_MASK  0x08000000 /**< PL configuration
 196                                                      *  reset
 197                                                      */
 198 #define XDCFG_IXR_AXI_WTO_MASK          0x00800000 /**< AXI Write Address
 199                                                      *  or Data or response
 200                                                      *  timeout
 201                                                      */
 202 #define XDCFG_IXR_AXI_WERR_MASK         0x00400000 /**< AXI Write response
 203                                                      *  error
 204                                                      */
 205 #define XDCFG_IXR_AXI_RTO_MASK          0x00200000 /**< AXI Read Address or
 206                                                      *  response timeout
 207                                                      */
 208 #define XDCFG_IXR_AXI_RERR_MASK         0x00100000 /**< AXI Read response
 209                                                      *  error
 210                                                      */
 211 #define XDCFG_IXR_RX_FIFO_OV_MASK       0x00040000 /**< Rx FIFO Overflow */
 212 #define XDCFG_IXR_WR_FIFO_LVL_MASK      0x00020000 /**< Tx FIFO less than
 213                                                      *  threshold */
 214 #define XDCFG_IXR_RD_FIFO_LVL_MASK      0x00010000 /**< Rx FIFO greater than
 215                                                      *  threshold */
 216 #define XDCFG_IXR_DMA_CMD_ERR_MASK      0x00008000 /**< Illegal DMA command */
 217 #define XDCFG_IXR_DMA_Q_OV_MASK         0x00004000 /**< DMA command queue
 218                                                      *  overflow
 219                                                      */
 220 #define XDCFG_IXR_DMA_DONE_MASK         0x00002000 /**< DMA Command Done */
 221 #define XDCFG_IXR_D_P_DONE_MASK         0x00001000 /**< DMA and PCAP
 222                                                      *  transfers Done
 223                                                      */
 224 #define XDCFG_IXR_P2D_LEN_ERR_MASK      0x00000800 /**< PCAP to DMA transfer
 225                                                      *  length error
 226                                                      */
 227 #define XDCFG_IXR_PCFG_HMAC_ERR_MASK    0x00000040 /**< HMAC error mask */
 228 #define XDCFG_IXR_PCFG_SEU_ERR_MASK     0x00000020 /**< SEU Error mask */
 229 #define XDCFG_IXR_PCFG_POR_B_MASK       0x00000010 /**< FPGA POR mask */
 230 #define XDCFG_IXR_PCFG_CFG_RST_MASK     0x00000008 /**< FPGA Reset mask */
 231 #define XDCFG_IXR_PCFG_DONE_MASK        0x00000004 /**< Done Signal  Mask */
 232 #define XDCFG_IXR_PCFG_INIT_PE_MASK     0x00000002 /**< Detect Positive edge
 233                                                      *  of Init Signal
 234                                                      */
 235 #define XDCFG_IXR_PCFG_INIT_NE_MASK     0x00000001 /**< Detect Negative edge
 236                                                      *  of Init Signal
 237                                                      */
 238 #define XDCFG_IXR_ERROR_FLAGS_MASK              (XDCFG_IXR_AXI_WTO_MASK | \
 239                                                 XDCFG_IXR_AXI_WERR_MASK | \
 240                                                 XDCFG_IXR_AXI_RTO_MASK |  \
 241                                                 XDCFG_IXR_AXI_RERR_MASK | \
 242                                                 XDCFG_IXR_RX_FIFO_OV_MASK | \
 243                                                 XDCFG_IXR_DMA_CMD_ERR_MASK |\
 244                                                 XDCFG_IXR_DMA_Q_OV_MASK |   \
 245                                                 XDCFG_IXR_P2D_LEN_ERR_MASK |\
 246                                                 XDCFG_IXR_PCFG_HMAC_ERR_MASK)
 247
 248
 249 #define XDCFG_IXR_ALL_MASK                      0x00F7F8EF
 250
 251
 252
 253 /* @} */
 254
 255
 256 /** @name Status Register Bit definitions
 257   * @{
 258  */
 259 #define XDCFG_STATUS_DMA_CMD_Q_F_MASK   0x80000000 /**< DMA command
 260                                                      *  Queue full
 261                                                      */
 262 #define XDCFG_STATUS_DMA_CMD_Q_E_MASK   0x40000000 /**< DMA command
 263                                                      *  Queue empty
 264                                                      */
 265 #define XDCFG_STATUS_DMA_DONE_CNT_MASK  0x30000000 /**< Number of
 266                                                      *  completed DMA
 267                                                      *  transfers
 268                                                      */
 269 #define XDCFG_STATUS_RX_FIFO_LVL_MASK   0x01F000000 /**< Rx FIFO level */
 270 #define XDCFG_STATUS_TX_FIFO_LVL_MASK   0x0007F000  /**< Tx FIFO level */
 271
 272 #define XDCFG_STATUS_PSS_GTS_USR_B      0x00000800  /**< Tri-state IO
 273                                                       *  during HIZ
 274                                                       */
 275 #define XDCFG_STATUS_PSS_FST_CFG_B      0x00000400  /**< First PL config
 276                                                       *  done
 277                                                       */
 278 #define XDCFG_STATUS_PSS_GPWRDWN_B      0x00000200  /**< Global power down */
 279 #define XDCFG_STATUS_PSS_GTS_CFG_B      0x00000100  /**< Tri-state IO during
 280                                                       *  config
 281                                                       */
 282 #define XDCFG_STATUS_SECURE_RST_MASK    0x00000080  /**< Secure Reset
 283                                                       *  POR Status
 284                                                       */
 285 #define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK    0x00000040 /**< Illegal APB
 286                                                              *  access
 287                                                              */
 288 #define XDCFG_STATUS_PSS_CFG_RESET_B            0x00000020 /**< PL config
 289                                                              *  reset status
 290                                                              */
 291 #define XDCFG_STATUS_PCFG_INIT_MASK             0x00000010 /**< FPGA Init
 292                                                              *  Status
 293                                                              */
 294 #define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK       0x00000008
 295                                                            /**< BBRAM key
 296                                                              *  disable
 297                                                              */
 298 #define XDCFG_STATUS_EFUSE_SEC_EN_MASK          0x00000004 /**< Efuse Security
 299                                                              *  Enable Status
 300                                                              */
 301 #define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK        0x00000002 /**< EFuse JTAG
 302                                                              *  Disable
 303                                                              *  status
 304                                                              */
 305 /* @} */
 306
 307
 308 /** @name DMA Source/Destination Transfer Length Register Bit definitions
 309  * @{
 310  */
 311 #define XDCFG_DMA_LEN_MASK              0x7FFFFFF /**< Length Mask */
 312 /*@}*/
 313
 314
 315
 316
 317 /** @name Miscellaneous Control  Register Bit definitions
 318   * @{
 319  */
 320 #define XDCFG_MCTRL_PCAP_PS_VERSION_MASK  0xF0000000 /**< PS Version Mask */
 321 #define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28         /**< PS Version Shift */
 322 #define XDCFG_MCTRL_PCAP_LPBK_MASK        0x00000010 /**< PCAP loopback mask */
 323 /* @} */
 324
 325 /** @name FIFO Threshold Bit definitions
 326   * @{
 327  */
 328
 329 #define XDCFG_CFG_FIFO_QUARTER          0x0      /**< Quarter empty */
 330 #define XDCFG_CFG_FIFO_HALF             0x1      /**< Half empty */
 331 #define XDCFG_CFG_FIFO_3QUARTER         0x2      /**< 3/4 empty */
 332 #define XDCFG_CFG_FIFO_EMPTY            0x4      /**< Empty */
 333 /* @}*/
 334
 335
 336 /* Miscellaneous constant values */
 337 #define XDCFG_DMA_INVALID_ADDRESS       0xFFFFFFFF  /**< Invalid DMA address */
 338 #define XDCFG_UNLOCK_DATA               0x757BDF0D  /**< First APB access data*/
 339 #define XDCFG_BASE_ADDRESS              0xF8007000  /**< Device Config base
 340                                                       * address
 341                                                       */
 342 #define XDCFG_CONFIG_RESET_VALUE        0x508   /**< Config reg reset value */
 343
 344 /**************************** Type Definitions *******************************/
 345
 346 /***************** Macros (Inline Functions) Definitions *********************/
 347
 348 /****************************************************************************/
 349 /**
 350 *
 351 * Read the given register.
 352 *
 353 * @param        BaseAddr is the base address of the device
 354 * @param        RegOffset is the register offset to be read
 355 *
 356 * @return       The 32-bit value of the register
 357 *
 358 * @note         C-style signature:
 359 *               u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
 360 *
 361 *****************************************************************************/
 362 #define XDcfg_ReadReg(BaseAddr, RegOffset)              \
 363         Xil_In32((BaseAddr) + (RegOffset))
 364
 365 /****************************************************************************/
 366 /**
 367 *
 368 * Write to the given register.
 369 *
 370 * @param        BaseAddr is the base address of the device
 371 * @param        RegOffset is the register offset to be written
 372 * @param        Data is the 32-bit value to write to the register
 373 *
 374 * @return       None.
 375 *
 376 * @note         C-style signature:
 377 *               void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
 378 *
 379 *****************************************************************************/
 380 #define XDcfg_WriteReg(BaseAddr, RegOffset, Data)       \
 381         Xil_Out32((BaseAddr) + (RegOffset), (Data))
 382
 383 /************************** Function Prototypes ******************************/
 384 /*
 385  * Perform reset operation to the devcfg interface
 386  */
 387 void XDcfg_ResetHw(u32 BaseAddr);
 388 /************************** Variable Definitions *****************************/
 389
 390 #ifdef __cplusplus
 391 }
 392 #endif
 393
 394 #endif  /* end of protection macro */
 395 /** @} */