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31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup devcfg_v3_5
39 * This file contains the implementation of the interface functions for XDcfg
40 * driver. Refer to the header file xdevcfg.h for more detailed information.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- --- -------- ---------------------------------------------
47 * 1.00a hvm 02/07/11 First release
48 * 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
49 * source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
50 * APIs is words (32 bit) and not bytes.
51 * Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
52 * to add information that 2 LSBs of the Source/Destination
53 * address when equal to 2�b01 indicate the last DMA command
54 * of an overall transfer.
55 * Updated the XDcfg_Transfer function to use the
56 * Destination Address passed to this API for secure transfers
57 * instead of using 0xFFFFFFFF for CR 662197. This issue was
58 * resulting in the failure of secure transfers of
59 * non-bitstream images.
60 * 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
61 * QUARTER_PCAP_RATE_EN bit in the control register for
62 * non secure writes for CR 675543.
63 * 2.02a nm 01/31/13 Fixed CR# 679335.
64 * Added Setting and Clearing the internal PCAP loopback.
65 * Removed code for enabling/disabling AES engine as BootROM
66 * locks down this setting.
68 * Skip Checking the PCFG_INIT in case of non-secure DMA
71 * XDcfg_Transfer fails to transfer data in loopback mode.
72 * 2.03a nm 04/19/13 Fixed CR# 703728.
73 * Updated the register definitions as per the latest TRM
74 * version UG585 (v1.4) November 16, 2012.
75 * 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
76 * 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
77 * updated driver code with != instead of ==,
78 * while checking for Interrupt Status with DMA and
80 * ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
81 * XDCFG_INT_STS_OFFSET) &
82 * XDCFG_IXR_D_P_DONE_MASK) !=
83 * XDCFG_IXR_D_P_DONE_MASK);
88 ******************************************************************************/
90 /***************************** Include Files *********************************/
94 /************************** Constant Definitions *****************************/
96 /**************************** Type Definitions *******************************/
98 /***************** Macros (Inline Functions) Definitions *********************/
100 /************************** Function Prototypes ******************************/
102 /************************** Variable Definitions *****************************/
104 /****************************************************************************/
107 * Initialize the Device Config Interface driver. This function
108 * must be called before other functions of the driver are called.
110 * @param InstancePtr is a pointer to the XDcfg instance.
111 * @param ConfigPtr is the config structure.
112 * @param EffectiveAddress is the base address for the device. It could be
113 * a virtual address if address translation is supported in the
114 * system, otherwise it is the physical address.
117 * - XST_SUCCESS if initialization was successful.
118 * - XST_DEVICE_IS_STARTED if the device has already been started.
120 * @note The very first APB access to the Device Configuration Interface
121 * block needs to be a write to the UNLOCK register with the value
122 * of 0x757BDF0D. This step is to be done once after reset, any
123 * other APB access has to come after this. The APB access is
124 * considered illegal if the step is not done or if it is done
125 * incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
126 * the following additional actions would be carried out.
127 * In other words, if all bits are low, the following steps are not
130 * 2. All APB writes disabled
131 * 3. SoC debug fully enabled
133 ******************************************************************************/
134 int XDcfg_CfgInitialize(XDcfg *InstancePtr,
135 XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
137 Xil_AssertNonvoid(InstancePtr != NULL);
138 Xil_AssertNonvoid(ConfigPtr != NULL);
141 * If the device is started, disallow the initialize and return a
142 * status indicating it is started. This allows the user to stop the
143 * device and reinitialize, but prevents a user from inadvertently
146 if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
147 return XST_DEVICE_IS_STARTED;
151 * Copy configuration into instance.
153 InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
156 * Save the base address pointer such that the registers of the block
157 * can be accessed and indicate it has not been started yet.
159 InstancePtr->Config.BaseAddr = EffectiveAddress;
160 InstancePtr->IsStarted = 0;
163 /* Unlock the Device Configuration Interface */
164 XDcfg_Unlock(InstancePtr);
167 * Indicate the instance is ready to use, successfully initialized.
169 InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
174 /****************************************************************************/
177 * The functions enables the PCAP interface by setting the PCAP mode bit in the
180 * @param InstancePtr is a pointer to the XDcfg instance.
184 * @note Enable FPGA programming from PCAP interface. Enabling this bit
185 * disables all the external interfaces from programming of FPGA
186 * except for ICAP. The user needs to ensure that the FPGA is
187 * programmed through either PCAP or ICAP.
189 *****************************************************************************/
190 void XDcfg_EnablePCAP(XDcfg *InstancePtr)
194 * Assert the arguments.
196 Xil_AssertVoid(InstancePtr != NULL);
197 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
200 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
203 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
204 (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
208 /****************************************************************************/
211 * The functions disables the PCAP interface by clearing the PCAP mode bit in
212 * the control register.
214 * @param InstancePtr is a pointer to the XDcfg instance.
220 *****************************************************************************/
221 void XDcfg_DisablePCAP(XDcfg *InstancePtr)
225 * Assert the arguments.
227 Xil_AssertVoid(InstancePtr != NULL);
228 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
231 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
234 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
235 (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
239 /****************************************************************************/
242 * The function sets the contents of the Control Register.
244 * @param InstancePtr is a pointer to the XDcfg instance.
245 * @param Mask is the 32 bit mask data to be written to the Register.
246 * The mask definitions are defined in the xdevcfg_hw.h file.
252 *****************************************************************************/
253 void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
257 * Assert the arguments.
259 Xil_AssertVoid(InstancePtr != NULL);
260 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
263 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
266 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
271 /****************************************************************************/
274 * The function Clears the specified bit positions of the Control Register.
276 * @param InstancePtr is a pointer to the XDcfg instance.
277 * @param Mask is the 32 bit value which holds the bit positions to be cleared.
283 *****************************************************************************/
284 void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
288 * Assert the arguments.
290 Xil_AssertVoid(InstancePtr != NULL);
291 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
294 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
297 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
302 /****************************************************************************/
305 * The function reads the contents of the Control Register.
307 * @param InstancePtr is a pointer to the XDcfg instance.
309 * @return A 32-bit value representing the contents of the Control
311 * Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
312 * interpret the returned value.
316 *****************************************************************************/
317 u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
320 * Assert the arguments.
322 Xil_AssertNonvoid(InstancePtr != NULL);
323 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
326 * Read the Control Register and return the value.
328 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
331 /****************************************************************************/
334 * The function sets the contents of the Lock Register. These bits
335 * can only be set to a 1. They will be cleared after a Power On Reset.
337 * @param InstancePtr is a pointer to the XDcfg instance.
338 * @param Data is the 32 bit data to be written to the Register.
344 *****************************************************************************/
345 void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
348 * Assert the arguments.
350 Xil_AssertVoid(InstancePtr != NULL);
351 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
353 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
357 /****************************************************************************/
360 * The function reads the contents of the Lock Register.
362 * @param InstancePtr is a pointer to the XDcfg instance.
364 * @return A 32-bit value representing the contents of the Lock
366 * Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
367 * interpret the returned value.
371 *****************************************************************************/
372 u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
375 * Assert the arguments.
377 Xil_AssertNonvoid(InstancePtr != NULL);
378 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
381 * Read the Lock Register and return the value.
383 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
386 /****************************************************************************/
389 * The function sets the contents of the Configuration Register with the
392 * @param InstancePtr is a pointer to the XDcfg instance.
393 * @param Data is the 32 bit data to be written to the Register.
399 *****************************************************************************/
400 void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
403 * Assert the arguments.
405 Xil_AssertVoid(InstancePtr != NULL);
406 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
408 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
412 /****************************************************************************/
415 * The function reads the contents of the Configuration Register with the
418 * @param InstancePtr is a pointer to the XDcfg instance.
420 * @return A 32-bit value representing the contents of the Config
422 * Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
423 * interpret the returned value.
427 *****************************************************************************/
428 u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
431 * Assert the arguments.
433 Xil_AssertNonvoid(InstancePtr != NULL);
434 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
436 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
440 /****************************************************************************/
443 * The function sets the contents of the Status Register.
445 * @param InstancePtr is a pointer to the XDcfg instance.
446 * @param Data is the 32 bit data to be written to the Register.
452 *****************************************************************************/
453 void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
456 * Assert the arguments.
458 Xil_AssertVoid(InstancePtr != NULL);
459 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
461 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
465 /****************************************************************************/
468 * The function reads the contents of the Status Register.
470 * @param InstancePtr is a pointer to the XDcfg instance.
472 * @return A 32-bit value representing the contents of the Status
474 * Use the XDCFG_STATUS_*_MASK constants defined in
475 * xdevcfg_hw.h to interpret the returned value.
479 *****************************************************************************/
480 u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
483 * Assert the arguments.
485 Xil_AssertNonvoid(InstancePtr != NULL);
486 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
489 * Read the Status Register and return the value.
491 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
494 /****************************************************************************/
497 * The function sets the contents of the ROM Shadow Control Register.
499 * @param InstancePtr is a pointer to the XDcfg instance.
500 * @param Data is the 32 bit data to be written to the Register.
504 * @note This register is can only be written and is used to control the
505 * RAM shadow of 32 bit 4K page ROM pages in user mode
507 *****************************************************************************/
508 void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
511 * Assert the arguments.
513 Xil_AssertVoid(InstancePtr != NULL);
514 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
516 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
521 /****************************************************************************/
524 * The function reads the contents of the Software ID Register.
526 * @param InstancePtr is a pointer to the XDcfg instance.
528 * @return 32 Bit boot software ID.
530 * @note This register is locked for write once the system enters
531 * usermode. Hence API for reading the register only is provided.
533 *****************************************************************************/
534 u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
537 * Assert the arguments.
539 Xil_AssertNonvoid(InstancePtr != NULL);
540 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
543 * Read the Software ID Register and return the value.
545 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
548 /****************************************************************************/
551 * The function sets the bit mask for the feature in Miscellaneous Control
554 * @param InstancePtr is a pointer to the XDcfg instance.
555 * @param Mask is the bit-mask of the feature to be set.
561 *****************************************************************************/
562 void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
567 * Assert the arguments.
569 Xil_AssertVoid(InstancePtr != NULL);
570 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
573 RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
576 XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
580 /****************************************************************************/
583 * The function reads the contents of the Miscellaneous Control Register.
585 * @param InstancePtr is a pointer to the XDcfg instance.
587 * @return 32 Bit boot software ID.
589 * @note This register is locked for write once the system enters
590 * usermode. Hence API to reading the register only is provided.
592 *****************************************************************************/
593 u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
596 * Assert the arguments.
598 Xil_AssertNonvoid(InstancePtr != NULL);
599 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
602 * Read the Miscellaneous Control Register and return the value.
604 return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
607 /******************************************************************************/
610 * This function checks if DMA command queue is full.
612 * @param InstancePtr is a pointer to the XDcfg instance.
614 * @return XST_SUCCESS is the DMA is busy
615 * XST_FAILURE if the DMA is idle
617 * @note The DMA queue has a depth of two.
619 ****************************************************************************/
620 u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
625 Xil_AssertNonvoid(InstancePtr != NULL);
626 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
628 /* Read the PCAP status register for DMA status */
629 RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
630 XDCFG_STATUS_OFFSET);
632 if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
633 XDCFG_STATUS_DMA_CMD_Q_F_MASK){
640 /******************************************************************************/
643 * This function initiates the DMA transfer.
645 * @param InstancePtr is a pointer to the XDcfg instance.
646 * @param SourcePtr contains a pointer to the source memory where the data
647 * is to be transferred from.
648 * @param SrcWordLength is the number of words (32 bit) to be transferred
649 * for the source transfer.
650 * @param DestPtr contains a pointer to the destination memory
651 * where the data is to be transferred to.
652 * @param DestWordLength is the number of words (32 bit) to be transferred
653 * for the Destination transfer.
657 * @note It is the responsibility of the caller function to ensure that
658 * correct values are passed to this function.
660 * The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
661 * address when equal to 2�b01 indicates the last DMA command of
662 * an overall transfer.
664 ****************************************************************************/
665 void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
666 u32 SrcWordLength, u32 DestWordLength)
669 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
670 XDCFG_DMA_SRC_ADDR_OFFSET,
673 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
674 XDCFG_DMA_DEST_ADDR_OFFSET,
677 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
678 XDCFG_DMA_SRC_LEN_OFFSET,
681 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
682 XDCFG_DMA_DEST_LEN_OFFSET,
686 /******************************************************************************/
689 * This function Implements the DMA Read Command. This command is used to
690 * transfer the image data from FPGA to the external memory.
692 * @param InstancePtr is a pointer to the XDcfg instance.
693 * @param SourcePtr contains a pointer to the source memory where the data
694 * is to be transferred from.
695 * @param SrcWordLength is the number of words (32 bit) to be transferred
696 * for the source transfer.
697 * @param DestPtr contains a pointer to the destination memory
698 * where the data is to be transferred to.
699 * @param DestWordLength is the number of words (32 bit) to be transferred
700 * for the Destination transfer.
702 * @return - XST_INVALID_PARAM if source address/length is invalid.
703 * - XST_SUCCESS if DMA transfer initiated properly.
707 ****************************************************************************/
708 static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
709 u32 SrcWordLength, u32 DestPtr,
715 * Send READ Frame command to FPGA
717 XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
721 * Store the enabled interrupts to enable before the actual read
722 * transfer is initiated and Disable all the interrupts temporarily.
724 IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
725 XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
728 * Wait till you get the DMA done for the read command sent
730 while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
731 XDCFG_INT_STS_OFFSET) &
732 XDCFG_IXR_D_P_DONE_MASK) !=
733 XDCFG_IXR_D_P_DONE_MASK);
735 * Enable the previously stored Interrupts .
737 XDcfg_IntrEnable(InstancePtr, IntrReg);
740 * Initiate the DMA write command.
742 XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
749 /****************************************************************************/
752 * This function starts the DMA transfer. This function only starts the
753 * operation and returns before the operation may be completed.
754 * If the interrupt is enabled, an interrupt will be generated when the
755 * operation is completed, otherwise it is necessary to poll the Status register
756 * to determine when it is completed. It is the responsibility of the caller to
757 * determine when the operation is completed by handling the generated interrupt
758 * or polling the Status Register.
760 * @param InstancePtr is a pointer to the XDcfg instance.
761 * @param SourcePtr contains a pointer to the source memory where the data
762 * is to be transferred from.
763 * @param SrcWordLength is the number of words (32 bit) to be transferred
764 * for the source transfer.
765 * @param DestPtr contains a pointer to the destination memory
766 * where the data is to be transferred to.
767 * @param DestWordLength is the number of words (32 bit) to be transferred
768 * for the Destination transfer.
769 * @param TransferType contains the type of PCAP transfer being requested.
770 * The definitions can be found in the xdevcfg.h file.
772 * - XST_SUCCESS.if DMA transfer initiated successfully
773 * - XST_DEVICE_BUSY if DMA is busy
774 * - XST_INVALID_PARAM if invalid Source / Destination address
775 * is sent or an invalid Source / Destination length is
778 * @note It is the responsibility of the caller to ensure that the cache
779 * is flushed and invalidated both before the DMA operation is
780 * started and after the DMA operation completes if the memory
781 * pointed to is cached. The caller must also ensure that the
782 * pointers contain physical address rather than a virtual address
783 * if address translation is being used.
785 * The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
786 * address when equal to 2�b01 indicates the last DMA command of
787 * an overall transfer.
789 *****************************************************************************/
790 u32 XDcfg_Transfer(XDcfg *InstancePtr,
791 void *SourcePtr, u32 SrcWordLength,
792 void *DestPtr, u32 DestWordLength,
798 Xil_AssertNonvoid(InstancePtr != NULL);
799 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
802 if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
803 return XST_DEVICE_BUSY;
807 * Check whether the fabric is in initialized state
809 if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
810 & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
812 * We don't need to check PCFG_INIT to be high for
813 * non-encrypted loopback transfers.
815 if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
820 if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
821 (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
823 /* Check for valid source pointer and length */
824 if ((!SourcePtr) || (SrcWordLength == 0)) {
825 return XST_INVALID_PARAM;
828 /* Clear internal PCAP loopback */
829 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
831 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
832 XDCFG_MCTRL_OFFSET, (CtrlReg &
833 ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
835 if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
837 * Clear QUARTER_PCAP_RATE_EN bit
838 * so that the PCAP data is transmitted every clock
840 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
843 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
844 XDCFG_CTRL_OFFSET, (CtrlReg &
845 ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
848 if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
850 * AES engine handles only 8 bit data every clock cycle.
851 * Hence, Encrypted PCAP data which is 32 bit data can
852 * only be sent in every 4 clock cycles. Set the control
853 * register QUARTER_PCAP_RATE_EN bit to achieve this
856 XDcfg_SetControlRegister(InstancePtr,
857 XDCFG_CTRL_PCAP_RATE_EN_MASK);
860 XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
861 (u32)DestPtr, SrcWordLength, DestWordLength);
865 if (TransferType == XDCFG_PCAP_READBACK) {
867 if ((!DestPtr) || (DestWordLength == 0)) {
869 return XST_INVALID_PARAM;
872 /* Clear internal PCAP loopback */
873 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
875 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
876 XDCFG_MCTRL_OFFSET, (CtrlReg &
877 ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
880 * For PCAP readback of FPGA configuration register or memory,
881 * the read command is first sent (written) to the FPGA fabric
882 * which responds by returning the required read data. Read data
883 * from the FPGA is captured if pcap_radata_v is active.A DMA
884 * read transfer is required to obtain the readback command,
885 * which is then sent to the FPGA, followed by a DMA write
886 * transfer to support this mode of operation.
888 return XDcfg_PcapReadback(InstancePtr,
889 (u32)SourcePtr, SrcWordLength,
890 (u32)DestPtr, DestWordLength);
894 if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
895 (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
897 if ((!SourcePtr) || (SrcWordLength == 0) ||
898 (!DestPtr) || (DestWordLength == 0)) {
899 return XST_INVALID_PARAM;
902 if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
903 /* Enable internal PCAP loopback */
904 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
906 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
907 XDCFG_MCTRL_OFFSET, (CtrlReg |
908 XDCFG_MCTRL_PCAP_LPBK_MASK));
911 * Clear QUARTER_PCAP_RATE_EN bit
912 * so that the PCAP data is transmitted every clock
914 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
917 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
918 XDCFG_CTRL_OFFSET, (CtrlReg &
919 ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
922 if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
923 /* Clear internal PCAP loopback */
924 CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
926 XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
927 XDCFG_MCTRL_OFFSET, (CtrlReg &
928 ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
931 * Set the QUARTER_PCAP_RATE_EN bit
932 * so that the PCAP data is transmitted every 4 clock
933 * cycles, this is required for encrypted data.
935 XDcfg_SetControlRegister(InstancePtr,
936 XDCFG_CTRL_PCAP_RATE_EN_MASK);
939 XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
940 (u32)DestPtr, SrcWordLength, DestWordLength);