1 /******************************************************************************
3 * Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup dmaps_v2_0
39 * This header file contains the hardware interface of an XDmaPs device.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ---- -------- ----------------------------------------------
46 * 1.00a hbm 08/18/10 First Release
47 * 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
48 * the maximum number of channels.
49 * Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
50 * with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
51 * 1.02a sg 05/16/12 Made changes for doxygen
52 * 1.06a kpc 07/10/13 Added function prototype
55 ******************************************************************************/
57 #ifndef XDMAPS_HW_H /* prevent circular inclusions */
58 #define XDMAPS_HW_H /* by using protection macros */
64 /***************************** Include Files *********************************/
66 #include "xil_types.h"
67 #include "xil_assert.h"
70 /************************** Constant Definitions *****************************/
72 /** @name Register Map
74 * Register offsets for the DMAC.
78 #define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
79 #define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
80 #define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
81 #define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
82 #define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
84 #define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
85 #define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
88 #define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
90 #define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
92 #define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
94 * The offset for the rest of the FTC registers is calculated as
95 * FTC0 + dev_chan_num * 4
97 #define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
99 #define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
101 * The offset for the rest of the CS registers is calculated as
102 * CS0 + * dev_chan_num * 0x08
104 #define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
106 #define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
110 * The offset for the rest of the CPC registers is calculated as
111 * CPC0 + dev_chan_num * 0x08
113 #define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
115 #define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
118 /* The offset for the rest of the SA registers is calculated as
119 * SA_0 + dev_chan_num * 0x20
121 #define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
123 #define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
126 /* The offset for the rest of the DA registers is calculated as
127 * DA_0 + dev_chan_num * 0x20
129 #define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
131 #define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
135 * The offset for the rest of the CC registers is calculated as
136 * CC_0 + dev_chan_num * 0x20
138 #define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
140 #define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
142 * The offset for the rest of the LC0 registers is calculated as
143 * LC_0 + dev_chan_num * 0x20
145 #define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
146 #define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
148 * The offset for the rest of the LC1 registers is calculated as
149 * LC_0 + dev_chan_num * 0x20
151 #define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
153 #define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
154 #define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
155 #define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
156 #define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
158 #define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
159 #define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
160 #define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
161 #define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
162 #define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
163 #define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
165 #define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
168 #define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
171 #define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
174 #define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
177 #define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
180 #define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
183 #define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
186 #define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
191 * Some useful register masks
193 #define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
194 #define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
196 #define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
198 #define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
199 * llast 3 bits of CS register
202 #define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
206 * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
207 * @b1: Instruction byte 1
208 * @b0: Instruction byte 0
209 * @ch: Channel number
210 * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
212 #define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
213 (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
217 /** @name Control Register
219 * The Control register (CR) controls the major functions of the device.
221 * Control Register Bit Definition
227 #define XDMAPS_CHANNELS_PER_DEV 8
230 /** @name Mode Register
232 * The mode register (MR) defines the mode of transfer as well as the data
233 * format. If this register is modified during transmission or reception,
234 * data validity cannot be guaranteed.
236 * Mode Register Bit Definition
243 /** @name Interrupt Registers
245 * Interrupt control logic uses the interrupt enable register (IER) and the
246 * interrupt disable register (IDR) to set the value of the bits in the
247 * interrupt mask register (IMR). The IMR determines whether to pass an
248 * interrupt to the interrupt status register (ISR).
249 * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
250 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
251 * Reading either IER or IDR returns 0x00.
253 * All four registers have the same bit definitions.
259 #define XDMAPS_INTCLR_ALL_MASK 0xFF
261 #define XDmaPs_ReadReg(BaseAddress, RegOffset) \
262 Xil_In32((BaseAddress) + (RegOffset))
264 /***************************************************************************/
266 * Write a DMAC register.
268 * @param BaseAddress contains the base address of the device.
269 * @param RegOffset contains the offset from the base address of the device.
270 * @param RegisterValue is the value to be written to the register.
276 * void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
278 ******************************************************************************/
279 #define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
280 Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
281 /************************** Variable Definitions *****************************/
283 /************************** Function Prototypes *****************************/
285 * Perform reset operation to the dmaps interface
287 void XDmaPs_ResetHw(u32 BaseAddr);
292 #endif /* end of protection macro */