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32 /*****************************************************************************/
36 * @addtogroup emacps_v2_0
39 * This file contains the implementation of the ethernet interface reset sequence
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ---- -------- -------------------------------------------------------
46 * 1.05a kpc 28/06/13 First release
49 ******************************************************************************/
51 /***************************** Include Files *********************************/
53 #include "xparameters.h"
54 #include "xemacps_hw.h"
56 /************************** Constant Definitions *****************************/
59 /**************************** Type Definitions *******************************/
62 /***************** Macros (Inline Functions) Definitions *********************/
65 /************************** Function Prototypes ******************************/
67 /*****************************************************************************/
69 * This function perform the reset sequence to the given emacps interface by
70 * configuring the appropriate control bits in the emacps specifc registers.
71 * the emacps reset squence involves the following steps
72 * Disable all the interuupts
73 * Clear the status registers
74 * Disable Rx and Tx engines
75 * Update the Tx and Rx descriptor queue registers with reset values
76 * Update the other relevant control registers with reset value
78 * @param BaseAddress of the interface
83 * This function will not modify the slcr registers that are relavant for
85 ******************************************************************************/
86 void XEmacPs_ResetHw(u32 BaseAddr)
90 /* Disable the interrupts */
91 XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0);
93 /* Stop transmission,disable loopback and Stop tx and Rx engines */
94 RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
95 RegVal &= ~(XEMACPS_NWCTRL_TXEN_MASK|
96 XEMACPS_NWCTRL_RXEN_MASK|
97 XEMACPS_NWCTRL_HALTTX_MASK|
98 XEMACPS_NWCTRL_LOOPEN_MASK);
99 /* Clear the statistic registers, flush the packets in DPRAM*/
100 RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
101 XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
102 XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
103 /* Clear the interrupt status */
104 XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
105 /* Clear the tx status */
106 XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,XEMACPS_TXSR_ERROR_MASK|
107 XEMACPS_TXSR_TXCOMPL_MASK|
108 XEMACPS_TXSR_TXGO_MASK);
109 /* Clear the rx status */
110 XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
111 XEMACPS_RXSR_FRAMERX_MASK);
112 /* Clear the tx base address */
113 XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0);
114 /* Clear the rx base address */
115 XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0);
116 /* Update the network config register with reset value */
117 XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
118 /* Update the hash address registers with reset value */
119 XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0);
120 XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0);