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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This header file contains identifiers and low-level driver functions (or
38 * macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
39 * High-level driver functions are defined in xemacps.h.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- -------------------------------------------------------
48 * 1.00a wsy 01/10/10 First release.
49 * 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
50 * 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
51 * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
52 * to 0x1fff. This fixes the CR#744902.
55 ******************************************************************************/
57 #ifndef XEMACPS_HW_H /* prevent circular inclusions */
58 #define XEMACPS_HW_H /* by using protection macros */
60 /***************************** Include Files *********************************/
62 #include "xil_types.h"
63 #include "xil_assert.h"
70 /************************** Constant Definitions *****************************/
72 #define XEMACPS_MAX_MAC_ADDR 4 /**< Maxmum number of mac address
74 #define XEMACPS_MAX_TYPE_ID 4 /**< Maxmum number of type id supported */
75 #define XEMACPS_BD_ALIGNMENT 4 /**< Minimum buffer descriptor alignment
77 #define XEMACPS_RX_BUF_ALIGNMENT 4 /**< Minimum buffer alignment when using
78 options that impose alignment
79 restrictions on the buffer data on
82 /** @name Direction identifiers
84 * These are used by several functions and callbacks that need
85 * to specify whether an operation specifies a send or receive channel.
88 #define XEMACPS_SEND 1 /**< send direction */
89 #define XEMACPS_RECV 2 /**< receive direction */
92 /** @name MDC clock division
93 * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
96 typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
97 MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
102 #define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in
103 bytes, 64, 128, ... 10240 */
104 #define XEMACPS_RX_BUF_UNIT 64 /**< Number of receive buffer bytes as a
105 unit, this is HW setup */
107 #define XEMACPS_MAX_RXBD 128 /**< Size of RX buffer descriptor queues */
108 #define XEMACPS_MAX_TXBD 128 /**< Size of TX buffer descriptor queues */
110 #define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */
112 /* Register offset definitions. Unless otherwise noted, register access is
113 * 32 bit. Names are self explained here.
116 #define XEMACPS_NWCTRL_OFFSET 0x00000000 /**< Network Control reg */
117 #define XEMACPS_NWCFG_OFFSET 0x00000004 /**< Network Config reg */
118 #define XEMACPS_NWSR_OFFSET 0x00000008 /**< Network Status reg */
120 #define XEMACPS_DMACR_OFFSET 0x00000010 /**< DMA Control reg */
121 #define XEMACPS_TXSR_OFFSET 0x00000014 /**< TX Status reg */
122 #define XEMACPS_RXQBASE_OFFSET 0x00000018 /**< RX Q Base address reg */
123 #define XEMACPS_TXQBASE_OFFSET 0x0000001C /**< TX Q Base address reg */
124 #define XEMACPS_RXSR_OFFSET 0x00000020 /**< RX Status reg */
126 #define XEMACPS_ISR_OFFSET 0x00000024 /**< Interrupt Status reg */
127 #define XEMACPS_IER_OFFSET 0x00000028 /**< Interrupt Enable reg */
128 #define XEMACPS_IDR_OFFSET 0x0000002C /**< Interrupt Disable reg */
129 #define XEMACPS_IMR_OFFSET 0x00000030 /**< Interrupt Mask reg */
131 #define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /**< Phy Maintaince reg */
132 #define XEMACPS_RXPAUSE_OFFSET 0x00000038 /**< RX Pause Time reg */
133 #define XEMACPS_TXPAUSE_OFFSET 0x0000003C /**< TX Pause Time reg */
135 #define XEMACPS_HASHL_OFFSET 0x00000080 /**< Hash Low address reg */
136 #define XEMACPS_HASHH_OFFSET 0x00000084 /**< Hash High address reg */
138 #define XEMACPS_LADDR1L_OFFSET 0x00000088 /**< Specific1 addr low reg */
139 #define XEMACPS_LADDR1H_OFFSET 0x0000008C /**< Specific1 addr high reg */
140 #define XEMACPS_LADDR2L_OFFSET 0x00000090 /**< Specific2 addr low reg */
141 #define XEMACPS_LADDR2H_OFFSET 0x00000094 /**< Specific2 addr high reg */
142 #define XEMACPS_LADDR3L_OFFSET 0x00000098 /**< Specific3 addr low reg */
143 #define XEMACPS_LADDR3H_OFFSET 0x0000009C /**< Specific3 addr high reg */
144 #define XEMACPS_LADDR4L_OFFSET 0x000000A0 /**< Specific4 addr low reg */
145 #define XEMACPS_LADDR4H_OFFSET 0x000000A4 /**< Specific4 addr high reg */
147 #define XEMACPS_MATCH1_OFFSET 0x000000A8 /**< Type ID1 Match reg */
148 #define XEMACPS_MATCH2_OFFSET 0x000000AC /**< Type ID2 Match reg */
149 #define XEMACPS_MATCH3_OFFSET 0x000000B0 /**< Type ID3 Match reg */
150 #define XEMACPS_MATCH4_OFFSET 0x000000B4 /**< Type ID4 Match reg */
152 #define XEMACPS_STRETCH_OFFSET 0x000000BC /**< IPG Stretch reg */
154 #define XEMACPS_OCTTXL_OFFSET 0x00000100 /**< Octects transmitted Low
156 #define XEMACPS_OCTTXH_OFFSET 0x00000104 /**< Octects transmitted High
159 #define XEMACPS_TXCNT_OFFSET 0x00000108 /**< Error-free Frmaes
160 transmitted counter */
161 #define XEMACPS_TXBCCNT_OFFSET 0x0000010C /**< Error-free Broadcast
163 #define XEMACPS_TXMCCNT_OFFSET 0x00000110 /**< Error-free Multicast
165 #define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /**< Pause Frames Transmitted
167 #define XEMACPS_TX64CNT_OFFSET 0x00000118 /**< Error-free 64 byte Frames
168 Transmitted counter */
169 #define XEMACPS_TX65CNT_OFFSET 0x0000011C /**< Error-free 65-127 byte
172 #define XEMACPS_TX128CNT_OFFSET 0x00000120 /**< Error-free 128-255 byte
175 #define XEMACPS_TX256CNT_OFFSET 0x00000124 /**< Error-free 256-511 byte
178 #define XEMACPS_TX512CNT_OFFSET 0x00000128 /**< Error-free 512-1023 byte
181 #define XEMACPS_TX1024CNT_OFFSET 0x0000012C /**< Error-free 1024-1518 byte
184 #define XEMACPS_TX1519CNT_OFFSET 0x00000130 /**< Error-free larger than
186 transmitted counter */
187 #define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /**< TX under run error
190 #define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /**< Single Collision Frame
192 #define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /**< Multiple Collision Frame
194 #define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame
196 #define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /**< Late Collision Frame
198 #define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /**< Deferred Transmission
200 #define XEMACPS_TXCSENSECNT_OFFSET 0x0000014C /**< Transmit Carrier Sense
203 #define XEMACPS_OCTRXL_OFFSET 0x00000150 /**< Octects Received register
205 #define XEMACPS_OCTRXH_OFFSET 0x00000154 /**< Octects Received register
208 #define XEMACPS_RXCNT_OFFSET 0x00000158 /**< Error-free Frames
210 #define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /**< Error-free Broadcast
211 Frames Received Counter */
212 #define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /**< Error-free Multicast
213 Frames Received Counter */
214 #define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /**< Pause Frames
216 #define XEMACPS_RX64CNT_OFFSET 0x00000168 /**< Error-free 64 byte Frames
218 #define XEMACPS_RX65CNT_OFFSET 0x0000016C /**< Error-free 65-127 byte
219 Frames Received Counter */
220 #define XEMACPS_RX128CNT_OFFSET 0x00000170 /**< Error-free 128-255 byte
221 Frames Received Counter */
222 #define XEMACPS_RX256CNT_OFFSET 0x00000174 /**< Error-free 256-512 byte
223 Frames Received Counter */
224 #define XEMACPS_RX512CNT_OFFSET 0x00000178 /**< Error-free 512-1023 byte
225 Frames Received Counter */
226 #define XEMACPS_RX1024CNT_OFFSET 0x0000017C /**< Error-free 1024-1518 byte
227 Frames Received Counter */
228 #define XEMACPS_RX1519CNT_OFFSET 0x00000180 /**< Error-free 1519-max byte
229 Frames Received Counter */
230 #define XEMACPS_RXUNDRCNT_OFFSET 0x00000184 /**< Undersize Frames Received
232 #define XEMACPS_RXOVRCNT_OFFSET 0x00000188 /**< Oversize Frames Received
234 #define XEMACPS_RXJABCNT_OFFSET 0x0000018C /**< Jabbers Received
236 #define XEMACPS_RXFCSCNT_OFFSET 0x00000190 /**< Frame Check Sequence
238 #define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194 /**< Length Field Error
240 #define XEMACPS_RXSYMBCNT_OFFSET 0x00000198 /**< Symbol Error Counter */
241 #define XEMACPS_RXALIGNCNT_OFFSET 0x0000019C /**< Alignment Error Counter */
242 #define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0 /**< Receive Resource Error
244 #define XEMACPS_RXORCNT_OFFSET 0x000001A4 /**< Receive Overrun Counter */
245 #define XEMACPS_RXIPCCNT_OFFSET 0x000001A8 /**< IP header Checksum Error
247 #define XEMACPS_RXTCPCCNT_OFFSET 0x000001AC /**< TCP Checksum Error
249 #define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0 /**< UDP Checksum Error
251 #define XEMACPS_LAST_OFFSET 0x000001B4 /**< Last statistic counter
252 offset, for clearing */
254 #define XEMACPS_1588_SEC_OFFSET 0x000001D0 /**< 1588 second counter */
255 #define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4 /**< 1588 nanosecond counter */
256 #define XEMACPS_1588_ADJ_OFFSET 0x000001D8 /**< 1588 nanosecond
257 adjustment counter */
258 #define XEMACPS_1588_INC_OFFSET 0x000001DC /**< 1588 nanosecond
260 #define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0 /**< 1588 PTP transmit second
262 #define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit
263 nanosecond counter */
264 #define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8 /**< 1588 PTP receive second
266 #define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive
267 nanosecond counter */
268 #define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0 /**< 1588 PTP peer transmit
270 #define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit
271 nanosecond counter */
272 #define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8 /**< 1588 PTP peer receive
274 #define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive
275 nanosecond counter */
277 /* Define some bit positions for registers. */
279 /** @name network control register bit definitions
282 #define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000 /**< Flush a packet from
284 #define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum
286 #define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800 /**< Transmit pause frame */
287 #define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400 /**< Halt transmission
288 after current frame */
289 #define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200 /**< Start tx (tx_go) */
291 #define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080 /**< Enable writing to
293 #define XEMACPS_NWCTRL_STATINC_MASK 0x00000040 /**< Increment statistic
295 #define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020 /**< Clear statistic
297 #define XEMACPS_NWCTRL_MDEN_MASK 0x00000010 /**< Enable MDIO port */
298 #define XEMACPS_NWCTRL_TXEN_MASK 0x00000008 /**< Enable transmit */
299 #define XEMACPS_NWCTRL_RXEN_MASK 0x00000004 /**< Enable receive */
300 #define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002 /**< local loopback */
303 /** @name network configuration register bit definitions
306 #define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of
307 non-standard preamble */
308 #define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000 /**< enable transmit IPG */
309 #define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000 /**< disable rejection of
311 #define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000 /**< RX half duplex */
312 #define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000 /**< enable RX checksum
314 #define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause
316 #define XEMACPS_NWCFG_MDC_SHIFT_MASK 18 /**< shift bits for MDC */
317 #define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000 /**< MDC Mask PCLK divisor */
318 #define XEMACPS_NWCFG_FCSREM_MASK 0x00020000 /**< Discard FCS from
320 #define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000
321 /**< RX length error discard */
322 #define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000 /**< RX buffer offset */
323 #define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000 /**< Enable pause RX */
324 #define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */
325 #define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200
326 /**< External address match enable */
327 #define XEMACPS_NWCFG_1000_MASK 0x00000400 /**< 1000 Mbps */
328 #define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100 /**< Enable 1536 byte
330 #define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash
332 #define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash
334 #define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020 /**< Do not receive
336 #define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010 /**< Copy all frames */
337 #define XEMACPS_NWCFG_JUMBO_MASK 0x00000008 /**< Jumbo frames */
338 #define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004 /**< Receive only VLAN
340 #define XEMACPS_NWCFG_FDEN_MASK 0x00000002 /**< full duplex */
341 #define XEMACPS_NWCFG_100_MASK 0x00000001 /**< 100 Mbps */
342 #define XEMACPS_NWCFG_RESET_MASK 0x00080000 /**< reset value */
345 /** @name network status register bit definitaions
348 #define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004 /**< PHY management idle */
349 #define XEMACPS_NWSR_MDIO_MASK 0x00000002 /**< Status of mdio_in */
353 /** @name MAC address register word 1 mask
356 #define XEMACPS_LADDR_MACH_MASK 0x0000FFFF /**< Address bits[47:32]
357 bit[31:0] are in BOTTOM */
361 /** @name DMA control register bit definitions
364 #define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000 /**< Mask bit for RX buffer
366 #define XEMACPS_DMACR_RXBUF_SHIFT 16 /**< Shift bit for RX buffer
368 #define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800 /**< enable/disable TX
370 #define XEMACPS_DMACR_TXSIZE_MASK 0x00000400 /**< TX buffer memory size */
371 #define XEMACPS_DMACR_RXSIZE_MASK 0x00000300 /**< RX buffer memory size */
372 #define XEMACPS_DMACR_ENDIAN_MASK 0x00000080 /**< endian configuration */
373 #define XEMACPS_DMACR_BLENGTH_MASK 0x0000001F /**< buffer burst length */
374 #define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001 /**< single AHB bursts */
375 #define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004 /**< 4 bytes AHB bursts */
376 #define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008 /**< 8 bytes AHB bursts */
377 #define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010 /**< 16 bytes AHB bursts */
380 /** @name transmit status register bit definitions
383 #define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100 /**< Transmit hresp not OK */
384 #define XEMACPS_TXSR_URUN_MASK 0x00000040 /**< Transmit underrun */
385 #define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020 /**< Transmit completed OK */
386 #define XEMACPS_TXSR_BUFEXH_MASK 0x00000010 /**< Transmit buffs exhausted
388 #define XEMACPS_TXSR_TXGO_MASK 0x00000008 /**< Status of go flag */
389 #define XEMACPS_TXSR_RXOVR_MASK 0x00000004 /**< Retry limit exceeded */
390 #define XEMACPS_TXSR_FRAMERX_MASK 0x00000002 /**< Collision tx frame */
391 #define XEMACPS_TXSR_USEDREAD_MASK 0x00000001 /**< TX buffer used bit set */
393 #define XEMACPS_TXSR_ERROR_MASK (XEMACPS_TXSR_HRESPNOK_MASK | \
394 XEMACPS_TXSR_URUN_MASK | \
395 XEMACPS_TXSR_BUFEXH_MASK | \
396 XEMACPS_TXSR_RXOVR_MASK | \
397 XEMACPS_TXSR_FRAMERX_MASK | \
398 XEMACPS_TXSR_USEDREAD_MASK)
402 * @name receive status register bit definitions
405 #define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008 /**< Receive hresp not OK */
406 #define XEMACPS_RXSR_RXOVR_MASK 0x00000004 /**< Receive overrun */
407 #define XEMACPS_RXSR_FRAMERX_MASK 0x00000002 /**< Frame received OK */
408 #define XEMACPS_RXSR_BUFFNA_MASK 0x00000001 /**< RX buffer used bit set */
410 #define XEMACPS_RXSR_ERROR_MASK (XEMACPS_RXSR_HRESPNOK_MASK | \
411 XEMACPS_RXSR_RXOVR_MASK | \
412 XEMACPS_RXSR_BUFFNA_MASK)
416 * @name interrupts bit definitions
417 * Bits definitions are same in XEMACPS_ISR_OFFSET,
418 * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
421 #define XEMACPS_IXR_PTPPSTX_MASK 0x02000000 /**< PTP Psync transmitted */
422 #define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000 /**< PTP Pdelay_req
424 #define XEMACPS_IXR_PTPSTX_MASK 0x00800000 /**< PTP Sync transmitted */
425 #define XEMACPS_IXR_PTPDRTX_MASK 0x00400000 /**< PTP Delay_req transmitted
427 #define XEMACPS_IXR_PTPPSRX_MASK 0x00200000 /**< PTP Psync received */
428 #define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000 /**< PTP Pdelay_req received */
429 #define XEMACPS_IXR_PTPSRX_MASK 0x00080000 /**< PTP Sync received */
430 #define XEMACPS_IXR_PTPDRRX_MASK 0x00040000 /**< PTP Delay_req received */
431 #define XEMACPS_IXR_PAUSETX_MASK 0x00004000 /**< Pause frame transmitted */
432 #define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000 /**< Pause time has reached
434 #define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000 /**< Pause frame received */
435 #define XEMACPS_IXR_HRESPNOK_MASK 0x00000800 /**< hresp not ok */
436 #define XEMACPS_IXR_RXOVR_MASK 0x00000400 /**< Receive overrun occurred */
437 #define XEMACPS_IXR_TXCOMPL_MASK 0x00000080 /**< Frame transmitted ok */
438 #define XEMACPS_IXR_TXEXH_MASK 0x00000040 /**< Transmit err occurred or
440 #define XEMACPS_IXR_RETRY_MASK 0x00000020 /**< Retry limit exceeded */
441 #define XEMACPS_IXR_URUN_MASK 0x00000010 /**< Transmit underrun */
442 #define XEMACPS_IXR_TXUSED_MASK 0x00000008 /**< Tx buffer used bit read */
443 #define XEMACPS_IXR_RXUSED_MASK 0x00000004 /**< Rx buffer used bit read */
444 #define XEMACPS_IXR_FRAMERX_MASK 0x00000002 /**< Frame received ok */
445 #define XEMACPS_IXR_MGMNT_MASK 0x00000001 /**< PHY management complete */
446 #define XEMACPS_IXR_ALL_MASK 0x00007FFF /**< Everything! */
448 #define XEMACPS_IXR_TX_ERR_MASK (XEMACPS_IXR_TXEXH_MASK | \
449 XEMACPS_IXR_RETRY_MASK | \
450 XEMACPS_IXR_URUN_MASK | \
451 XEMACPS_IXR_TXUSED_MASK)
454 #define XEMACPS_IXR_RX_ERR_MASK (XEMACPS_IXR_HRESPNOK_MASK | \
455 XEMACPS_IXR_RXUSED_MASK | \
456 XEMACPS_IXR_RXOVR_MASK)
460 /** @name PHY Maintenance bit definitions
463 #define XEMACPS_PHYMNTNC_OP_MASK 0x40020000 /**< operation mask bits */
464 #define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000 /**< read operation */
465 #define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000 /**< write operation */
466 #define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000 /**< Address bits */
467 #define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000 /**< register bits */
468 #define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFF /**< data bits */
469 #define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /**< Shift bits for PHYAD */
470 #define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK 18 /**< Shift bits for PHREG */
473 /* Transmit buffer descriptor status words offset
476 #define XEMACPS_BD_ADDR_OFFSET 0x00000000 /**< word 0/addr of BDs */
477 #define XEMACPS_BD_STAT_OFFSET 0x00000004 /**< word 1/status of BDs */
482 /* Transmit buffer descriptor status words bit positions.
483 * Transmit buffer descriptor consists of two 32-bit registers,
484 * the first - word0 contains a 32-bit address pointing to the location of
486 * The following register - word1, consists of various information to control
487 * the XEmacPs transmit process. After transmit, this is updated with status
488 * information, whether the frame was transmitted OK or why it had failed.
491 #define XEMACPS_TXBUF_USED_MASK 0x80000000 /**< Used bit. */
492 #define XEMACPS_TXBUF_WRAP_MASK 0x40000000 /**< Wrap bit, last descriptor */
493 #define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */
494 #define XEMACPS_TXBUF_URUN_MASK 0x10000000 /**< Transmit underrun occurred */
495 #define XEMACPS_TXBUF_EXH_MASK 0x08000000 /**< Buffers exhausted */
496 #define XEMACPS_TXBUF_TCP_MASK 0x04000000 /**< Late collision. */
497 #define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */
498 #define XEMACPS_TXBUF_LAST_MASK 0x00008000 /**< Last buffer */
499 #define XEMACPS_TXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */
504 /* Receive buffer descriptor status words bit positions.
505 * Receive buffer descriptor consists of two 32-bit registers,
506 * the first - word0 contains a 32-bit word aligned address pointing to the
507 * address of the buffer. The lower two bits make up the wrap bit indicating
508 * the last descriptor and the ownership bit to indicate it has been used by
510 * The following register - word1, contains status information regarding why
511 * the frame was received (the filter match condition) as well as other
515 #define XEMACPS_RXBUF_BCAST_MASK 0x80000000 /**< Broadcast frame */
516 #define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */
517 #define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000 /**< Unicast hashed frame */
518 #define XEMACPS_RXBUF_EXH_MASK 0x08000000 /**< buffer exhausted */
519 #define XEMACPS_RXBUF_AMATCH_MASK 0x06000000 /**< Specific address
521 #define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000 /**< Type ID matched */
522 #define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000 /**< ID matched mask */
523 #define XEMACPS_RXBUF_VLAN_MASK 0x00200000 /**< VLAN tagged */
524 #define XEMACPS_RXBUF_PRI_MASK 0x00100000 /**< Priority tagged */
525 #define XEMACPS_RXBUF_VPRI_MASK 0x000E0000 /**< Vlan priority */
526 #define XEMACPS_RXBUF_CFI_MASK 0x00010000 /**< CFI frame */
527 #define XEMACPS_RXBUF_EOF_MASK 0x00008000 /**< End of frame. */
528 #define XEMACPS_RXBUF_SOF_MASK 0x00004000 /**< Start of frame. */
529 #define XEMACPS_RXBUF_LEN_MASK 0x00001FFF /**< Mask for length field */
531 #define XEMACPS_RXBUF_WRAP_MASK 0x00000002 /**< Wrap bit, last BD */
532 #define XEMACPS_RXBUF_NEW_MASK 0x00000001 /**< Used bit.. */
533 #define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /**< Mask for address */
539 * Define appropriate I/O access method to mempry mapped I/O or other
540 * intarfce if necessary.
543 #define XEmacPs_In32 Xil_In32
544 #define XEmacPs_Out32 Xil_Out32
547 /****************************************************************************/
550 * Read the given register.
552 * @param BaseAddress is the base address of the device
553 * @param RegOffset is the register offset to be read
555 * @return The 32-bit value of the register
559 * u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
561 *****************************************************************************/
562 #define XEmacPs_ReadReg(BaseAddress, RegOffset) \
563 XEmacPs_In32((BaseAddress) + (RegOffset))
566 /****************************************************************************/
569 * Write the given register.
571 * @param BaseAddress is the base address of the device
572 * @param RegOffset is the register offset to be written
573 * @param Data is the 32-bit value to write to the register
579 * void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
582 *****************************************************************************/
583 #define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
584 XEmacPs_Out32((BaseAddress) + (RegOffset), (Data))
586 /************************** Function Prototypes *****************************/
588 * Perform reset operation to the emacps interface
590 void XEmacPs_ResetHw(u32 BaseAddr);
596 #endif /* end of protection macro */