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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpiops_v2_1
39 * The XGpioPs driver. Functions in this file are the minimum required functions
40 * for this driver. See xgpiops.h for a detailed description of the driver.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- ---- -------- -----------------------------------------------
47 * 1.00a sv 01/15/10 First Release
48 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
49 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
50 * relevant to Zynq device. The interrupts are disabled
51 * for output pins on all banks during initialization.
52 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
56 ******************************************************************************/
58 /***************************** Include Files *********************************/
62 /************************** Constant Definitions *****************************/
64 /**************************** Type Definitions *******************************/
66 /***************** Macros (Inline Functions) Definitions *********************/
68 /************************** Variable Definitions *****************************/
71 * This structure defines the mapping of the pin numbers to the banks when
72 * the driver APIs are used for working on the individual pins.
74 unsigned int XGpioPsPinTable[] = {
75 31, /* 0 - 31, Bank 0 */
76 53, /* 32 - 53, Bank 1 */
77 85, /* 54 - 85, Bank 2 */
78 117 /* 86 - 117 Bank 3 */
81 /************************** Function Prototypes ******************************/
83 extern void StubHandler(void *CallBackRef, int Bank, u32 Status);
85 /*****************************************************************************/
88 * This function initializes a XGpioPs instance/driver.
89 * All members of the XGpioPs instance structure are initialized and
90 * StubHandlers are assigned to the Bank Status Handlers.
92 * @param InstancePtr is a pointer to the XGpioPs instance.
93 * @param ConfigPtr points to the XGpioPs device configuration structure.
94 * @param EffectiveAddr is the device base address in the virtual memory
95 * address space. If the address translation is not used then the
96 * physical address should be passed.
97 * Unexpected errors may occur if the address mapping is changed
98 * after this function is invoked.
100 * @return XST_SUCCESS always.
104 ******************************************************************************/
105 int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
109 Xil_AssertNonvoid(InstancePtr != NULL);
110 Xil_AssertNonvoid(ConfigPtr != NULL);
113 * Set some default values for instance data, don't indicate the device
114 * is ready to use until everything has been initialized successfully.
116 InstancePtr->IsReady = 0;
117 InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
118 InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
119 InstancePtr->Handler = StubHandler;
122 * By default, interrupts are not masked in GPIO. Disable
123 * interrupts for all pins in all the 4 banks.
125 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
126 XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
128 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
129 ((1) * XGPIOPS_REG_MASK_OFFSET) +
130 XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
132 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
133 ((2) * XGPIOPS_REG_MASK_OFFSET) +
134 XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
136 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
137 ((3) * XGPIOPS_REG_MASK_OFFSET) +
138 XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
141 * Indicate the component is now ready to use.
143 InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
148 /****************************************************************************/
151 * Read the Data register of the specified GPIO bank.
153 * @param InstancePtr is a pointer to the XGpioPs instance.
154 * @param Bank is the bank number of the GPIO to operate on.
155 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
157 * @return Current value of the Data register.
159 * @note This function is used for reading the state of all the GPIO pins
162 *****************************************************************************/
163 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
165 Xil_AssertNonvoid(InstancePtr != NULL);
166 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
167 Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
169 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
170 ((Bank) * XGPIOPS_DATA_BANK_OFFSET) +
171 XGPIOPS_DATA_RO_OFFSET);
174 /****************************************************************************/
177 * Read Data from the specified pin.
179 * @param InstancePtr is a pointer to the XGpioPs instance.
180 * @param Pin is the pin number for which the data has to be read.
181 * Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
182 * See xgpiops.h for the mapping of the pin numbers in the banks.
184 * @return Current value of the Pin (0 or 1).
186 * @note This function is used for reading the state of the specified
189 *****************************************************************************/
190 int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin)
195 Xil_AssertNonvoid(InstancePtr != NULL);
196 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
197 Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
200 * Get the Bank number and Pin number within the bank.
202 XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
204 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
205 ((Bank) * XGPIOPS_DATA_BANK_OFFSET) +
206 XGPIOPS_DATA_RO_OFFSET) >> PinNumber) & 1;
210 /****************************************************************************/
213 * Write to the Data register of the specified GPIO bank.
215 * @param InstancePtr is a pointer to the XGpioPs instance.
216 * @param Bank is the bank number of the GPIO to operate on.
217 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
218 * @param Data is the value to be written to the Data register.
222 * @note This function is used for writing to all the GPIO pins of
223 * the bank. The previous state of the pins is not maintained.
225 *****************************************************************************/
226 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
228 Xil_AssertVoid(InstancePtr != NULL);
229 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
230 Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
232 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
233 ((Bank) * XGPIOPS_DATA_BANK_OFFSET) +
234 XGPIOPS_DATA_OFFSET, Data);
237 /****************************************************************************/
240 * Write data to the specified pin.
242 * @param InstancePtr is a pointer to the XGpioPs instance.
243 * @param Pin is the pin number to which the Data is to be written.
244 * Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
245 * @param Data is the data to be written to the specified pin (0 or 1).
249 * @note This function does a masked write to the specified pin of
250 * the specified GPIO bank. The previous state of other pins
253 *****************************************************************************/
254 void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data)
261 Xil_AssertVoid(InstancePtr != NULL);
262 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
263 Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
266 * Get the Bank number and Pin number within the bank.
268 XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
270 if (PinNumber > 15) {
272 * There are only 16 data bits in bit maskable register.
275 RegOffset = XGPIOPS_DATA_MSW_OFFSET;
277 RegOffset = XGPIOPS_DATA_LSW_OFFSET;
281 * Get the 32 bit value to be written to the Mask/Data register where
282 * the upper 16 bits is the mask and lower 16 bits is the data.
285 Value = ~(1 << (PinNumber + 16)) & ((Data << PinNumber) | 0xFFFF0000);
286 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
287 ((Bank) * XGPIOPS_DATA_MASK_OFFSET) +
293 /****************************************************************************/
296 * Set the Direction of the pins of the specified GPIO Bank.
298 * @param InstancePtr is a pointer to the XGpioPs instance.
299 * @param Bank is the bank number of the GPIO to operate on.
300 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
301 * @param Direction is the 32 bit mask of the Pin direction to be set for
302 * all the pins in the Bank. Bits with 0 are set to Input mode,
303 * bits with 1 are set to Output Mode.
307 * @note This function is used for setting the direction of all the pins
308 * in the specified bank. The previous state of the pins is
311 *****************************************************************************/
312 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
314 Xil_AssertVoid(InstancePtr != NULL);
315 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
316 Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
318 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
319 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
320 XGPIOPS_DIRM_OFFSET, Direction);
323 /****************************************************************************/
326 * Set the Direction of the specified pin.
328 * @param InstancePtr is a pointer to the XGpioPs instance.
329 * @param Pin is the pin number to which the Data is to be written.
330 * Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
331 * @param Direction is the direction to be set for the specified pin.
332 * Valid values are 0 for Input Direction, 1 for Output Direction.
336 *****************************************************************************/
337 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction)
343 Xil_AssertVoid(InstancePtr != NULL);
344 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
345 Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
346 Xil_AssertVoid((Direction == 0) || (Direction == 1));
349 * Get the Bank number and Pin number within the bank.
351 XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
353 DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
354 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
355 XGPIOPS_DIRM_OFFSET);
357 if (Direction) { /* Output Direction */
358 DirModeReg |= (1 << PinNumber);
359 } else { /* Input Direction */
360 DirModeReg &= ~ (1 << PinNumber);
363 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
364 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
365 XGPIOPS_DIRM_OFFSET, DirModeReg);
368 /****************************************************************************/
371 * Get the Direction of the pins of the specified GPIO Bank.
373 * @param InstancePtr is a pointer to the XGpioPs instance.
374 * @param Bank is the bank number of the GPIO to operate on.
375 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
377 * return Returns a 32 bit mask of the Direction register. Bits with 0 are
378 * in Input mode, bits with 1 are in Output Mode.
382 *****************************************************************************/
383 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
385 Xil_AssertNonvoid(InstancePtr != NULL);
386 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
387 Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
389 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
390 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
391 XGPIOPS_DIRM_OFFSET);
394 /****************************************************************************/
397 * Get the Direction of the specified pin.
399 * @param InstancePtr is a pointer to the XGpioPs instance.
400 * @param Pin is the pin number for which the Direction is to be
402 * Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
404 * @return Direction of the specified pin.
405 * - 0 for Input Direction
406 * - 1 for Output Direction
410 *****************************************************************************/
411 int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin)
416 Xil_AssertNonvoid(InstancePtr != NULL);
417 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
418 Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
421 * Get the Bank number and Pin number within the bank.
423 XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
425 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
426 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
427 XGPIOPS_DIRM_OFFSET) >> PinNumber) & 1;
430 /****************************************************************************/
433 * Set the Output Enable of the pins of the specified GPIO Bank.
435 * @param InstancePtr is a pointer to the XGpioPs instance.
436 * @param Bank is the bank number of the GPIO to operate on.
437 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
438 * @param OpEnable is the 32 bit mask of the Output Enables to be set for
439 * all the pins in the Bank. The Output Enable of bits with 0 are
440 * disabled, the Output Enable of bits with 1 are enabled.
444 * @note This function is used for setting the Output Enables of all the
445 * pins in the specified bank. The previous state of the Output
446 * Enables is not maintained.
448 *****************************************************************************/
449 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
451 Xil_AssertVoid(InstancePtr != NULL);
452 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
453 Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
455 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
456 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
457 XGPIOPS_OUTEN_OFFSET, OpEnable);
460 /****************************************************************************/
463 * Set the Output Enable of the specified pin.
465 * @param InstancePtr is a pointer to the XGpioPs instance.
466 * @param Pin is the pin number to which the Data is to be written.
467 * Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
468 * @param OpEnable specifies whether the Output Enable for the specified
469 * pin should be enabled.
470 * Valid values are 0 for Disabling Output Enable,
471 * 1 for Enabling Output Enable.
477 *****************************************************************************/
478 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int OpEnable)
484 Xil_AssertVoid(InstancePtr != NULL);
485 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
486 Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
487 Xil_AssertVoid((OpEnable == 0) || (OpEnable == 1));
490 * Get the Bank number and Pin number within the bank.
492 XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
494 OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
495 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
496 XGPIOPS_OUTEN_OFFSET);
498 if (OpEnable) { /* Enable Output Enable */
499 OpEnableReg |= (1 << PinNumber);
500 } else { /* Disable Output Enable */
501 OpEnableReg &= ~ (1 << PinNumber);
504 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
505 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
506 XGPIOPS_OUTEN_OFFSET, OpEnableReg);
508 /****************************************************************************/
511 * Get the Output Enable status of the pins of the specified GPIO Bank.
513 * @param InstancePtr is a pointer to the XGpioPs instance.
514 * @param Bank is the bank number of the GPIO to operate on.
515 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
517 * return Returns a a 32 bit mask of the Output Enable register.
518 * Bits with 0 are in Disabled state, bits with 1 are in
523 *****************************************************************************/
524 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
526 Xil_AssertNonvoid(InstancePtr != NULL);
527 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
528 Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
530 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
531 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
532 XGPIOPS_OUTEN_OFFSET);
535 /****************************************************************************/
538 * Get the Output Enable status of the specified pin.
540 * @param InstancePtr is a pointer to the XGpioPs instance.
541 * @param Pin is the pin number for which the Output Enable status is to
543 * Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
545 * @return Output Enable of the specified pin.
546 * - 0 if Output Enable is disabled for this pin
547 * - 1 if Output Enable is enabled for this pin
551 *****************************************************************************/
552 int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin)
557 Xil_AssertNonvoid(InstancePtr != NULL);
558 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
559 Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
562 * Get the Bank number and Pin number within the bank.
564 XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
566 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
567 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
568 XGPIOPS_OUTEN_OFFSET) >> PinNumber) & 1;
571 /****************************************************************************/
574 * Get the Bank number and the Pin number in the Bank, for the given PinNumber
575 * in the GPIO device.
577 * @param PinNumber is the Pin number in the GPIO device.
578 * @param BankNumber returns the Bank in which this GPIO pin is present.
579 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
580 * @param PinNumberInBank returns the Pin Number within the Bank.
586 *****************************************************************************/
587 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
589 for (*BankNumber = 0; *BankNumber < 4; (*BankNumber)++)
590 if (PinNumber <= XGpioPsPinTable[*BankNumber])
593 if (*BankNumber == 0) {
594 *PinNumberInBank = PinNumber;
596 *PinNumberInBank = PinNumber %
597 (XGpioPsPinTable[*BankNumber - 1] + 1);