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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpiops_v2_1
39 * This header file contains the identifiers and basic driver functions (or
40 * macros) that can be used to access the device. Other driver functions
41 * are defined in xgpiops.h.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- -------------------------------------------------
48 * 1.00a sv 01/15/10 First Release
49 * 1.02a hk 08/22/13 Added low level reset API function prototype and
50 * related constant definitions
53 ******************************************************************************/
54 #ifndef XGPIOPS_HW_H /* prevent circular inclusions */
55 #define XGPIOPS_HW_H /* by using protection macros */
59 #endif /* __cplusplus */
61 /***************************** Include Files *********************************/
63 #include "xil_types.h"
64 #include "xil_assert.h"
67 /************************** Constant Definitions *****************************/
69 /** @name Register offsets for the GPIO. Each register is 32 bits.
72 #define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */
73 #define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */
74 #define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */
75 #define XGPIOPS_DATA_RO_OFFSET 0x060 /* Data Register - Input, RO */
76 #define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */
77 #define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */
78 #define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */
79 #define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */
80 #define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/
81 #define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */
82 #define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */
83 #define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */
84 #define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */
87 /** @name Register offsets for each Bank.
90 #define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */
91 #define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */
92 #define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */
95 /* For backwards compatibility */
96 #define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET
98 /** @name Interrupt type reset values for each bank
101 #define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF
102 #define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF
103 #define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF
104 #define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF
107 /**************************** Type Definitions *******************************/
109 /***************** Macros (Inline Functions) Definitions *********************/
111 /****************************************************************************/
114 * This macro reads the given register.
116 * @param BaseAddr is the base address of the device.
117 * @param RegOffset is the register offset to be read.
119 * @return The 32-bit value of the register
123 *****************************************************************************/
124 #define XGpioPs_ReadReg(BaseAddr, RegOffset) \
125 Xil_In32((BaseAddr) + (RegOffset))
127 /****************************************************************************/
130 * This macro writes to the given register.
132 * @param BaseAddr is the base address of the device.
133 * @param RegOffset is the offset of the register to be written.
134 * @param Data is the 32-bit value to write to the register.
140 *****************************************************************************/
141 #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
142 Xil_Out32((BaseAddr) + (RegOffset), (Data))
144 /************************** Function Prototypes ******************************/
146 void XGpioPs_ResetHw(u32 BaseAddress);
150 #endif /* __cplusplus */
152 #endif /* XGPIOPS_HW_H */