1 /******************************************************************************
3 * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup gpiops_v3_1
39 * The XGpioPs driver. Functions in this file are the minimum required functions
40 * for this driver. See xgpiops.h for a detailed description of the driver.
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- ---- -------- -----------------------------------------------
47 * 1.00a sv 01/15/10 First Release
48 * 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
49 * XGpioPs_GetMode, XGpioPs_GetModePin as they are not
50 * relevant to Zynq device. The interrupts are disabled
51 * for output pins on all banks during initialization.
52 * 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
53 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
54 * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
58 ******************************************************************************/
60 /***************************** Include Files *********************************/
64 /************************** Constant Definitions *****************************/
66 /**************************** Type Definitions *******************************/
68 /***************** Macros (Inline Functions) Definitions *********************/
70 /************************** Variable Definitions *****************************/
73 /************************** Function Prototypes ******************************/
75 extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
77 /*****************************************************************************/
80 * This function initializes a XGpioPs instance/driver.
81 * All members of the XGpioPs instance structure are initialized and
82 * StubHandlers are assigned to the Bank Status Handlers.
84 * @param InstancePtr is a pointer to the XGpioPs instance.
85 * @param ConfigPtr points to the XGpioPs device configuration structure.
86 * @param EffectiveAddr is the device base address in the virtual memory
87 * address space. If the address translation is not used then the
88 * physical address should be passed.
89 * Unexpected errors may occur if the address mapping is changed
90 * after this function is invoked.
92 * @return XST_SUCCESS always.
96 ******************************************************************************/
97 s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
100 s32 Status = XST_SUCCESS;
102 Xil_AssertNonvoid(InstancePtr != NULL);
103 Xil_AssertNonvoid(ConfigPtr != NULL);
104 Xil_AssertNonvoid(EffectiveAddr != (u32)0);
106 * Set some default values for instance data, don't indicate the device
107 * is ready to use until everything has been initialized successfully.
109 InstancePtr->IsReady = 0U;
110 InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
111 InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
112 InstancePtr->Handler = StubHandler;
113 InstancePtr->Platform = XGetPlatform_Info();
115 /* Initialize the Bank data based on platform */
116 if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
118 * Max pins in the ZynqMP GPIO device
126 InstancePtr->MaxPinNum = (u32)174;
127 InstancePtr->MaxBanks = (u8)6;
130 * Max pins in the GPIO device
136 InstancePtr->MaxPinNum = (u32)118;
137 InstancePtr->MaxBanks = (u8)4;
141 * By default, interrupts are not masked in GPIO. Disable
142 * interrupts for all pins in all the 4 banks.
144 for (i=0;i<InstancePtr->MaxBanks;i++) {
145 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
146 ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
147 XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
150 /* Indicate the component is now ready to use. */
151 InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
156 /****************************************************************************/
159 * Read the Data register of the specified GPIO bank.
161 * @param InstancePtr is a pointer to the XGpioPs instance.
162 * @param Bank is the bank number of the GPIO to operate on.
163 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
165 * @return Current value of the Data register.
167 * @note This function is used for reading the state of all the GPIO pins
170 *****************************************************************************/
171 u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
173 Xil_AssertNonvoid(InstancePtr != NULL);
174 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
175 Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
177 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
178 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
179 XGPIOPS_DATA_RO_OFFSET);
182 /****************************************************************************/
185 * Read Data from the specified pin.
187 * @param InstancePtr is a pointer to the XGpioPs instance.
188 * @param Pin is the pin number for which the data has to be read.
189 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
190 * See xgpiops.h for the mapping of the pin numbers in the banks.
192 * @return Current value of the Pin (0 or 1).
194 * @note This function is used for reading the state of the specified
197 *****************************************************************************/
198 u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
203 Xil_AssertNonvoid(InstancePtr != NULL);
204 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
205 Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
207 /* Get the Bank number and Pin number within the bank. */
208 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
210 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
211 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
212 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
216 /****************************************************************************/
219 * Write to the Data register of the specified GPIO bank.
221 * @param InstancePtr is a pointer to the XGpioPs instance.
222 * @param Bank is the bank number of the GPIO to operate on.
223 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
224 * @param Data is the value to be written to the Data register.
228 * @note This function is used for writing to all the GPIO pins of
229 * the bank. The previous state of the pins is not maintained.
231 *****************************************************************************/
232 void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
234 Xil_AssertVoid(InstancePtr != NULL);
235 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
236 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
238 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
239 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
240 XGPIOPS_DATA_OFFSET, Data);
243 /****************************************************************************/
246 * Write data to the specified pin.
248 * @param InstancePtr is a pointer to the XGpioPs instance.
249 * @param Pin is the pin number to which the Data is to be written.
250 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
251 * @param Data is the data to be written to the specified pin (0 or 1).
255 * @note This function does a masked write to the specified pin of
256 * the specified GPIO bank. The previous state of other pins
259 *****************************************************************************/
260 void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
268 Xil_AssertVoid(InstancePtr != NULL);
269 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
270 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
272 /* Get the Bank number and Pin number within the bank. */
273 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
275 if (PinNumber > 15U) {
276 /* There are only 16 data bits in bit maskable register. */
278 RegOffset = XGPIOPS_DATA_MSW_OFFSET;
280 RegOffset = XGPIOPS_DATA_LSW_OFFSET;
284 * Get the 32 bit value to be written to the Mask/Data register where
285 * the upper 16 bits is the mask and lower 16 bits is the data.
287 DataVar &= (u32)0x01;
288 Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
289 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
290 ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
296 /****************************************************************************/
299 * Set the Direction of the pins of the specified GPIO Bank.
301 * @param InstancePtr is a pointer to the XGpioPs instance.
302 * @param Bank is the bank number of the GPIO to operate on.
303 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
304 * @param Direction is the 32 bit mask of the Pin direction to be set for
305 * all the pins in the Bank. Bits with 0 are set to Input mode,
306 * bits with 1 are set to Output Mode.
310 * @note This function is used for setting the direction of all the pins
311 * in the specified bank. The previous state of the pins is
314 *****************************************************************************/
315 void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
317 Xil_AssertVoid(InstancePtr != NULL);
318 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
319 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
321 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
322 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
323 XGPIOPS_DIRM_OFFSET, Direction);
326 /****************************************************************************/
329 * Set the Direction of the specified pin.
331 * @param InstancePtr is a pointer to the XGpioPs instance.
332 * @param Pin is the pin number to which the Data is to be written.
333 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
334 * @param Direction is the direction to be set for the specified pin.
335 * Valid values are 0 for Input Direction, 1 for Output Direction.
339 *****************************************************************************/
340 void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
346 Xil_AssertVoid(InstancePtr != NULL);
347 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
348 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
349 Xil_AssertVoid(Direction <= (u32)1);
351 /* Get the Bank number and Pin number within the bank. */
352 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
354 DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
355 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
356 XGPIOPS_DIRM_OFFSET);
358 if (Direction!=(u32)0) { /* Output Direction */
359 DirModeReg |= ((u32)1 << (u32)PinNumber);
360 } else { /* Input Direction */
361 DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
364 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
365 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
366 XGPIOPS_DIRM_OFFSET, DirModeReg);
369 /****************************************************************************/
372 * Get the Direction of the pins of the specified GPIO Bank.
374 * @param InstancePtr is a pointer to the XGpioPs instance.
375 * @param Bank is the bank number of the GPIO to operate on.
376 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
378 * return Returns a 32 bit mask of the Direction register. Bits with 0 are
379 * in Input mode, bits with 1 are in Output Mode.
383 *****************************************************************************/
384 u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
386 Xil_AssertNonvoid(InstancePtr != NULL);
387 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
388 Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
390 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
391 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
392 XGPIOPS_DIRM_OFFSET);
395 /****************************************************************************/
398 * Get the Direction of the specified pin.
400 * @param InstancePtr is a pointer to the XGpioPs instance.
401 * @param Pin is the pin number for which the Direction is to be
403 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
405 * @return Direction of the specified pin.
406 * - 0 for Input Direction
407 * - 1 for Output Direction
411 *****************************************************************************/
412 u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
417 Xil_AssertNonvoid(InstancePtr != NULL);
418 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
419 Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
421 /* Get the Bank number and Pin number within the bank. */
422 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
424 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
425 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
426 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
429 /****************************************************************************/
432 * Set the Output Enable of the pins of the specified GPIO Bank.
434 * @param InstancePtr is a pointer to the XGpioPs instance.
435 * @param Bank is the bank number of the GPIO to operate on.
436 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
437 * @param OpEnable is the 32 bit mask of the Output Enables to be set for
438 * all the pins in the Bank. The Output Enable of bits with 0 are
439 * disabled, the Output Enable of bits with 1 are enabled.
443 * @note This function is used for setting the Output Enables of all the
444 * pins in the specified bank. The previous state of the Output
445 * Enables is not maintained.
447 *****************************************************************************/
448 void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
450 Xil_AssertVoid(InstancePtr != NULL);
451 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
452 Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
454 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
455 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
456 XGPIOPS_OUTEN_OFFSET, OpEnable);
459 /****************************************************************************/
462 * Set the Output Enable of the specified pin.
464 * @param InstancePtr is a pointer to the XGpioPs instance.
465 * @param Pin is the pin number to which the Data is to be written.
466 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
467 * @param OpEnable specifies whether the Output Enable for the specified
468 * pin should be enabled.
469 * Valid values are 0 for Disabling Output Enable,
470 * 1 for Enabling Output Enable.
476 *****************************************************************************/
477 void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
483 Xil_AssertVoid(InstancePtr != NULL);
484 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
485 Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
486 Xil_AssertVoid(OpEnable <= (u32)1);
488 /* Get the Bank number and Pin number within the bank. */
489 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
491 OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
492 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
493 XGPIOPS_OUTEN_OFFSET);
495 if (OpEnable != (u32)0) { /* Enable Output Enable */
496 OpEnableReg |= ((u32)1 << (u32)PinNumber);
497 } else { /* Disable Output Enable */
498 OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
501 XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
502 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
503 XGPIOPS_OUTEN_OFFSET, OpEnableReg);
505 /****************************************************************************/
508 * Get the Output Enable status of the pins of the specified GPIO Bank.
510 * @param InstancePtr is a pointer to the XGpioPs instance.
511 * @param Bank is the bank number of the GPIO to operate on.
512 * Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
514 * return Returns a a 32 bit mask of the Output Enable register.
515 * Bits with 0 are in Disabled state, bits with 1 are in
520 *****************************************************************************/
521 u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
523 Xil_AssertNonvoid(InstancePtr != NULL);
524 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
525 Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
527 return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
528 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
529 XGPIOPS_OUTEN_OFFSET);
532 /****************************************************************************/
535 * Get the Output Enable status of the specified pin.
537 * @param InstancePtr is a pointer to the XGpioPs instance.
538 * @param Pin is the pin number for which the Output Enable status is to
540 * Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
542 * @return Output Enable of the specified pin.
543 * - 0 if Output Enable is disabled for this pin
544 * - 1 if Output Enable is enabled for this pin
548 *****************************************************************************/
549 u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
554 Xil_AssertNonvoid(InstancePtr != NULL);
555 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
556 Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
558 /* Get the Bank number and Pin number within the bank. */
559 XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
561 return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
562 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
563 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
566 /****************************************************************************/
569 * Get the Bank number and the Pin number in the Bank, for the given PinNumber
570 * in the GPIO device.
572 * @param PinNumber is the Pin number in the GPIO device.
573 * @param BankNumber returns the Bank in which this GPIO pin is present.
574 * Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
575 * @param PinNumberInBank returns the Pin Number within the Bank.
581 *****************************************************************************/
582 void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
584 u32 XGpioPsPinTable[6] = {0};
585 u32 Platform = XGetPlatform_Info();
587 if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
589 * This structure defines the mapping of the pin numbers to the banks when
590 * the driver APIs are used for working on the individual pins.
593 XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
594 XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
595 XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
596 XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
597 XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
598 XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
601 while (*BankNumber < 6U) {
602 if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
608 XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
609 XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
610 XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
611 XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
614 while (*BankNumber < 4U) {
615 if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
621 if (*BankNumber == (u8)0) {
622 *PinNumberInBank = PinNumber;
624 *PinNumberInBank = (u8)((u32)PinNumber %
625 (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));