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31 ******************************************************************************/
32 /*****************************************************************************/
37 * Contains implementation of required functions for providing the reset sequence
38 * to the i2c interface
40 * <pre> MODIFICATION HISTORY:
42 * Ver Who Date Changes
43 * ----- ------ -------- --------------------------------------------
44 * 1.04a kpc 11/07/13 First release
48 ******************************************************************************/
50 /***************************** Include Files *********************************/
52 #include "xiicps_hw.h"
54 /************************** Constant Definitions *****************************/
56 /**************************** Type Definitions *******************************/
58 /***************** Macros (Inline Functions) Definitions *********************/
60 /************************** Function Prototypes ******************************/
62 /************************** Variable Definitions *****************************/
63 /*****************************************************************************/
65 * This function perform the reset sequence to the given I2c interface by
66 * configuring the appropriate control bits in the I2c specifc registers
67 * the i2cps reset squence involves the following steps
68 * Disable all the interuupts
70 * Clear FIFO's and disable hold bit
71 * Clear the line status
72 * Update relevant config registers with reset values
74 * @param BaseAddress of the interface
79 * This function will not modify the slcr registers that are relavant for
81 ******************************************************************************/
82 void XIicPs_ResetHw(u32 BaseAddress)
86 /* Disable all the interrupts */
87 XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
88 /* Clear the interrupt status */
89 RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
90 XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
91 /* Clear the hold bit,master enable bit and ack bit */
92 RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
93 RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
95 RegVal |= XIICPS_CR_CLR_FIFO_MASK;
96 XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
97 /* Clear the timeout register */
98 XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, 0x0);
99 /* Clear the transfer size register */
100 XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0);
101 /* Clear the status register */
102 RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
103 XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
104 /* Update the configuraqtion register with reset value */
105 XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0);