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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup iicps_v2_1
39 * This header file contains the hardware definition for an IIC device.
40 * It includes register definitions and interface functions to read/write
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ------ -------- -----------------------------------------------
48 * 1.00a drg/jz 01/30/10 First release
49 * 1.04a kpc 11/07/13 Added function prototype.
52 ******************************************************************************/
53 #ifndef XIICPS_HW_H /* prevent circular inclusions */
54 #define XIICPS_HW_H /* by using protection macros */
60 /***************************** Include Files *********************************/
62 #include "xil_types.h"
63 #include "xil_assert.h"
66 /************************** Constant Definitions *****************************/
68 /** @name Register Map
70 * Register offsets for the IIC.
73 #define XIICPS_CR_OFFSET 0x00 /**< 32-bit Control */
74 #define XIICPS_SR_OFFSET 0x04 /**< Status */
75 #define XIICPS_ADDR_OFFSET 0x08 /**< IIC Address */
76 #define XIICPS_DATA_OFFSET 0x0C /**< IIC FIFO Data */
77 #define XIICPS_ISR_OFFSET 0x10 /**< Interrupt Status */
78 #define XIICPS_TRANS_SIZE_OFFSET 0x14 /**< Transfer Size */
79 #define XIICPS_SLV_PAUSE_OFFSET 0x18 /**< Slave monitor pause */
80 #define XIICPS_TIME_OUT_OFFSET 0x1C /**< Time Out */
81 #define XIICPS_IMR_OFFSET 0x20 /**< Interrupt Enabled Mask */
82 #define XIICPS_IER_OFFSET 0x24 /**< Interrupt Enable */
83 #define XIICPS_IDR_OFFSET 0x28 /**< Interrupt Disable */
86 /** @name Control Register
88 * This register contains various control bits that
89 * affects the operation of the IIC controller. Read/Write.
93 #define XIICPS_CR_DIV_A_MASK 0x0000C000 /**< Clock Divisor A */
94 #define XIICPS_CR_DIV_A_SHIFT 14 /**< Clock Divisor A shift */
95 #define XIICPS_DIV_A_MAX 4 /**< Maximum value of Divisor A */
96 #define XIICPS_CR_DIV_B_MASK 0x00003F00 /**< Clock Divisor B */
97 #define XIICPS_CR_DIV_B_SHIFT 8 /**< Clock Divisor B shift */
98 #define XIICPS_CR_CLR_FIFO_MASK 0x00000040 /**< Clear FIFO, auto clears*/
99 #define XIICPS_CR_SLVMON_MASK 0x00000020 /**< Slave monitor mode */
100 #define XIICPS_CR_HOLD_MASK 0x00000010 /**< Hold bus 1=Hold scl,
101 0=terminate transfer */
102 #define XIICPS_CR_ACKEN_MASK 0x00000008 /**< Enable TX of ACK when
104 #define XIICPS_CR_NEA_MASK 0x00000004 /**< Addressing Mode 1=7 bit,
106 #define XIICPS_CR_MS_MASK 0x00000002 /**< Master mode bit 1=Master,
108 #define XIICPS_CR_RD_WR_MASK 0x00000001 /**< Read or Write Master
109 transfer 0=Transmitter,
111 #define XIICPS_CR_RESET_VALUE 0 /**< Reset value of the Control
115 /** @name IIC Status Register
117 * This register is used to indicate status of the IIC controller. Read only
120 #define XIICPS_SR_BA_MASK 0x00000100 /**< Bus Active Mask */
121 #define XIICPS_SR_RXOVF_MASK 0x00000080 /**< Receiver Overflow Mask */
122 #define XIICPS_SR_TXDV_MASK 0x00000040 /**< Transmit Data Valid Mask */
123 #define XIICPS_SR_RXDV_MASK 0x00000020 /**< Receiver Data Valid Mask */
124 #define XIICPS_SR_RXRW_MASK 0x00000008 /**< Receive read/write Mask */
127 /** @name IIC Address Register
129 * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
130 * A write access to this register always initiates a transfer if the IIC is in
131 * master mode. Read/Write
134 #define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
137 /** @name IIC Data Register
139 * When written to, the data register sets data to transmit. When read from, the
140 * data register reads the last received byte of data. Read/Write
143 #define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
146 /** @name IIC Interrupt Registers
148 * <b>IIC Interrupt Status Register</b>
150 * This register holds the interrupt status flags for the IIC controller. Some
151 * of the flags are level triggered
152 * - i.e. are set as long as the interrupt condition exists. Other flags are
153 * edge triggered, which means they are set one the interrupt condition occurs
154 * then remain set until they are cleared by software.
155 * The interrupts are cleared by writing a one to the interrupt bit position
156 * in the Interrupt Status Register. Read/Write.
158 * <b>IIC Interrupt Enable Register</b>
160 * This register is used to enable interrupt sources for the IIC controller.
161 * Writing a '1' to a bit in this register clears the corresponding bit in the
162 * IIC Interrupt Mask register. Write only.
164 * <b>IIC Interrupt Disable Register </b>
166 * This register is used to disable interrupt sources for the IIC controller.
167 * Writing a '1' to a bit in this register sets the corresponding bit in the
168 * IIC Interrupt Mask register. Write only.
170 * <b>IIC Interrupt Mask Register</b>
172 * This register shows the enabled/disabled status of each IIC controller
173 * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
174 * the status register. A bit set to 0 means the interrupt is enabled.
175 * All mask bits are set and all interrupts are disabled after reset. Read only.
177 * All four registers have the same bit definitions. They are only defined once
178 * for each of the Interrupt Enable Register, Interrupt Disable Register,
179 * Interrupt Mask Register, and Interrupt Status Register
183 #define XIICPS_IXR_ARB_LOST_MASK 0x00000200 /**< Arbitration Lost Interrupt
185 #define XIICPS_IXR_RX_UNF_MASK 0x00000080 /**< FIFO Recieve Underflow
187 #define XIICPS_IXR_TX_OVR_MASK 0x00000040 /**< Transmit Overflow
189 #define XIICPS_IXR_RX_OVR_MASK 0x00000020 /**< Receive Overflow Interrupt
191 #define XIICPS_IXR_SLV_RDY_MASK 0x00000010 /**< Monitored Slave Ready
193 #define XIICPS_IXR_TO_MASK 0x00000008 /**< Transfer Time Out
195 #define XIICPS_IXR_NACK_MASK 0x00000004 /**< NACK Interrupt mask */
196 #define XIICPS_IXR_DATA_MASK 0x00000002 /**< Data Interrupt mask */
197 #define XIICPS_IXR_COMP_MASK 0x00000001 /**< Transfer Complete
199 #define XIICPS_IXR_DEFAULT_MASK 0x000002FF /**< Default ISR Mask */
200 #define XIICPS_IXR_ALL_INTR_MASK 0x000002FF /**< All ISR Mask */
204 /** @name IIC Transfer Size Register
206 * The register's meaning varies according to the operating mode as follows:
207 * - Master transmitter mode: number of data bytes still not transmitted minus
209 * - Master receiver mode: number of data bytes that are still expected to be
211 * - Slave transmitter mode: number of bytes remaining in the FIFO after the
212 * master terminates the transfer
213 * - Slave receiver mode: number of valid data bytes in the FIFO
215 * This register is cleared if CLR_FIFO bit in the control register is set.
219 #define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
220 #define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
221 #define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
225 /** @name IIC Slave Monitor Pause Register
227 * This register is associated with the slave monitor mode of the I2C interface.
228 * It is meaningful only when the module is in master mode and bit SLVMON in the
229 * control register is set.
231 * This register defines the pause interval between consecutive attempts to
232 * address the slave once a write to an I2C address register is done by the
233 * host. It represents the number of sclk cycles minus one between two attempts.
235 * The reset value of the register is 0, which results in the master repeatedly
236 * trying to access the slave immediately after unsuccessful attempt.
240 #define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
244 /** @name IIC Time Out Register
246 * The value of time out register represents the time out interval in number of
247 * sclk cycles minus one.
249 * When the accessed slave holds the sclk line low for longer than the time out
250 * period, thus prohibiting the I2C interface in master mode to complete the
251 * current transfer, an interrupt is generated and TO interrupt flag is set.
253 * The reset value of the register is 0x1f.
257 #define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */
258 #define XIICPS_TO_RESET_VALUE 0x0000001F /**< IIC Time Out reset value */
261 /**************************** Type Definitions *******************************/
263 /***************** Macros (Inline Functions) Definitions *********************/
265 #define XIicPs_In32 Xil_In32
266 #define XIicPs_Out32 Xil_Out32
268 /****************************************************************************/
270 * Read an IIC register.
272 * @param BaseAddress contains the base address of the device.
273 * @param RegOffset contains the offset from the 1st register of the
274 * device to select the specific register.
276 * @return The value read from the register.
278 * @note C-Style signature:
279 * u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
281 ******************************************************************************/
282 #define XIicPs_ReadReg(BaseAddress, RegOffset) \
283 XIicPs_In32((BaseAddress) + (RegOffset))
285 /***************************************************************************/
287 * Write an IIC register.
289 * @param BaseAddress contains the base address of the device.
290 * @param RegOffset contains the offset from the 1st register of the
291 * device to select the specific register.
292 * @param RegisterValue is the value to be written to the register.
296 * @note C-Style signature:
297 * void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
299 ******************************************************************************/
300 #define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
301 XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
303 /***************************************************************************/
305 * Read the interrupt enable register.
307 * @param BaseAddress contains the base address of the device.
309 * @return Current bit mask that represents currently enabled interrupts.
311 * @note C-Style signature:
312 * u32 XIicPs_ReadIER(u32 BaseAddress)
314 ******************************************************************************/
315 #define XIicPs_ReadIER(BaseAddress) \
316 XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
318 /***************************************************************************/
320 * Write to the interrupt enable register.
322 * @param BaseAddress contains the base address of the device.
324 * @param IntrMask is the interrupts to be enabled.
328 * @note C-Style signature:
329 * void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
331 ******************************************************************************/
332 #define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
333 XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
335 /***************************************************************************/
337 * Disable all interrupts.
339 * @param BaseAddress contains the base address of the device.
343 * @note C-Style signature:
344 * void XIicPs_DisableAllInterrupts(u32 BaseAddress)
346 ******************************************************************************/
347 #define XIicPs_DisableAllInterrupts(BaseAddress) \
348 XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
349 XIICPS_IXR_ALL_INTR_MASK)
351 /***************************************************************************/
353 * Disable selected interrupts.
355 * @param BaseAddress contains the base address of the device.
357 * @param IntrMask is the interrupts to be disabled.
361 * @note C-Style signature:
362 * void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
364 ******************************************************************************/
365 #define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
366 XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
369 /************************** Variable Definitions *****************************/
371 /************************** Function Prototypes ******************************/
373 * Perform reset operation to the I2c interface
375 void XIicPs_ResetHw(u32 BaseAddr);
380 #endif /* end of protection macro */