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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup iicps_v3_5
39 * Contains implementation of required functions for the XIicPs driver.
40 * See xiicps.h for detailed description of the device and driver.
42 * <pre> MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- ------ -------- --------------------------------------------
46 * 1.00a drg/jz 01/30/10 First release
47 * 1.00a sdm 09/21/11 Updated the InstancePtr->Options in the
48 * XIicPs_CfgInitialize by calling XIicPs_GetOptions.
49 * 2.1 hk 04/25/14 Explicitly reset CR and clear FIFO in Abort function
50 * and state the same in the comments. CR# 784254.
51 * Fix for CR# 761060 - provision for repeated start.
52 * 2.3 sk 10/07/14 Repeated start feature removed.
53 * 3.0 sk 11/03/14 Modified TimeOut Register value to 0xFF
55 * 12/06/14 Implemented Repeated start feature.
56 * 01/31/15 Modified the code according to MISRAC 2012 Compliant.
57 * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
61 ******************************************************************************/
63 /***************************** Include Files *********************************/
67 /************************** Constant Definitions *****************************/
69 /**************************** Type Definitions *******************************/
71 /***************** Macros (Inline Functions) Definitions *********************/
73 /************************** Function Prototypes ******************************/
75 static void StubHandler(void *CallBackRef, u32 StatusEvent);
77 /************************** Variable Definitions *****************************/
80 /*****************************************************************************/
83 * Initializes a specific XIicPs instance such that the driver is ready to use.
85 * The state of the device after initialization is:
86 * - Device is disabled
89 * @param InstancePtr is a pointer to the XIicPs instance.
90 * @param ConfigPtr is a reference to a structure containing information
91 * about a specific IIC device. This function initializes an
92 * InstancePtr object for a specific device specified by the
94 * @param EffectiveAddr is the device base address in the virtual memory
95 * address space. The caller is responsible for keeping the address
96 * mapping from EffectiveAddr to the device physical base address
97 * unchanged once this function is invoked. Unexpected errors may
98 * occur if the address mapping changes after this function is
99 * called. If address translation is not used, use
100 * ConfigPtr->BaseAddress for this parameter, passing the physical
103 * @return The return value is XST_SUCCESS if successful.
107 ******************************************************************************/
108 s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
112 * Assert validates the input arguments.
114 Xil_AssertNonvoid(InstancePtr != NULL);
115 Xil_AssertNonvoid(ConfigPtr != NULL);
118 * Set some default values.
120 InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
121 InstancePtr->Config.BaseAddress = EffectiveAddr;
122 InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
123 InstancePtr->StatusHandler = StubHandler;
124 InstancePtr->CallBackRef = NULL;
126 InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
129 * Reset the IIC device to get it into its initial state. It is expected
130 * that device configuration will take place after this initialization
131 * is done, but before the device is started.
133 XIicPs_Reset(InstancePtr);
136 * Keep a copy of what options this instance has.
138 InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
140 /* Initialize repeated start flag to 0 */
141 InstancePtr->IsRepeatedStart = 0;
143 return (s32)XST_SUCCESS;
146 /*****************************************************************************/
148 * Check whether the I2C bus is busy
150 * @param InstancePtr is a pointer to the XIicPs instance.
153 * - TRUE if the bus is busy.
154 * - FALSE if the bus is not busy.
158 ******************************************************************************/
159 s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
164 StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
166 if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
174 /*****************************************************************************/
177 * This is a stub for the status callback. The stub is here in case the upper
178 * layers forget to set the handler.
180 * @param CallBackRef is a pointer to the upper layer callback reference.
181 * @param StatusEvent is the event that just occurred.
182 * @param ByteCount is the number of bytes transferred up until the event
189 ******************************************************************************/
190 static void StubHandler(void *CallBackRef, u32 StatusEvent)
192 (void) ((void *)CallBackRef);
194 Xil_AssertVoidAlways();
198 /*****************************************************************************/
201 * Aborts a transfer in progress by resetting the FIFOs. The byte counts are
204 * @param InstancePtr is a pointer to the XIicPs instance.
210 ******************************************************************************/
211 void XIicPs_Abort(XIicPs *InstancePtr)
216 Xil_AssertVoid(InstancePtr != NULL);
217 Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
220 * Enter a critical section, so disable the interrupts while we clear
221 * the FIFO and the status register.
223 IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
225 XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
226 XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
229 * Reset the settings in config register and clear the FIFOs.
231 XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
232 (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
235 * Read, then write the interrupt status to make sure there are no
236 * pending interrupts.
238 IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
240 XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
241 XIICPS_ISR_OFFSET, IntrStatusReg);
244 * Restore the interrupt state.
246 IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
247 XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
248 XIICPS_IER_OFFSET, IntrMaskReg);
252 /*****************************************************************************/
255 * Resets the IIC device. Reset must only be called after the driver has been
256 * initialized. The configuration of the device after reset is the same as its
257 * configuration after initialization. Any data transfer that is in progress is
260 * The upper layer software is responsible for re-configuring (if necessary)
261 * and reenabling interrupts for the IIC device after the reset.
263 * @param InstancePtr is a pointer to the XIicPs instance.
269 ******************************************************************************/
270 void XIicPs_Reset(XIicPs *InstancePtr)
273 Xil_AssertVoid(InstancePtr != NULL);
274 Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
277 * Abort any transfer that is in progress.
279 XIicPs_Abort(InstancePtr);
282 * Reset any values so the software state matches the hardware device.
284 XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
285 XIICPS_CR_RESET_VALUE);
286 XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
287 XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
288 XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
289 XIICPS_IXR_ALL_INTR_MASK);
292 /*****************************************************************************/
294 * Put more data into the transmit FIFO, number of bytes is ether expected
295 * number of bytes for this transfer or available space in FIFO, which ever
298 * @param InstancePtr is a pointer to the XIicPs instance.
300 * @return Number of bytes left for this instance.
302 * @note This is function is shared by master and slave.
304 ******************************************************************************/
305 s32 TransmitFifoFill(XIicPs *InstancePtr)
312 * Determine number of bytes to write to FIFO.
314 AvailBytes = (u8)XIICPS_FIFO_DEPTH -
315 (u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
316 XIICPS_TRANS_SIZE_OFFSET);
318 if (InstancePtr->SendByteCount > (s32)AvailBytes) {
319 NumBytesToSend = (s32)AvailBytes;
321 NumBytesToSend = InstancePtr->SendByteCount;
325 * Fill FIFO with amount determined above.
327 for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
328 XIicPs_SendByte(InstancePtr);
331 return InstancePtr->SendByteCount;