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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xqspips_hw.c
  36 *
  37 * Contains low level functions, primarily reset related.
  38 *
  39 * <pre>
  40 * MODIFICATION HISTORY:
  41 *
  42 * Ver   Who Date     Changes
  43 * ----- --- -------- -----------------------------------------------
  44 * 2.03a hk  09/17/13 First release
  45 *
  46 * </pre>
  47 *
  48 ******************************************************************************/
  49
  50 /***************************** Include Files *********************************/
  51
  52 #include "xqspips_hw.h"
  53 #include "xqspips.h"
  54
  55 /************************** Constant Definitions *****************************/
  56
  57 /** @name Pre-scaler value for divided by 4
  58  *
  59  * Pre-scaler value for divided by 4
  60  *
  61  * @{
  62  */
  63 #define XQSPIPS_CR_PRESC_DIV_BY_4       0x01
  64 /* @} */
  65
  66 /**************************** Type Definitions *******************************/
  67
  68 /***************** Macros (Inline Functions) Definitions *********************/
  69
  70 /************************** Function Prototypes ******************************/
  71
  72 /************************** Variable Definitions *****************************/
  73
  74
  75 /*****************************************************************************/
  76 /**
  77 *
  78 * Resets QSPI by disabling the device and bringing it to reset state through
  79 * register writes.
  80 *
  81 * @param        None
  82 *
  83 * @return       None.
  84 *
  85 * @note         None.
  86 *
  87 ******************************************************************************/
  88 void XQspiPs_ResetHw(u32 BaseAddress)
  89 {
  90         u32 ConfigReg;
  91
  92         /*
  93          * Disable interrupts
  94          */
  95         XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
  96                                 XQSPIPS_IXR_DISABLE_ALL);
  97
  98         /*
  99          * Disable device
 100          */
 101         XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
 102                                 0);
 103
 104         /*
 105          * De-assert slave select lines.
 106          */
 107         ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
 108         ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
 109         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
 110
 111         /*
 112          * Write default value to RX and TX threshold registers
 113          * RX threshold should be set to 1 here because the corresponding
 114          * status bit is used next to clear the RXFIFO
 115          */
 116         XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
 117                         (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
 118         XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
 119                         (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
 120
 121         /*
 122          * Clear RXFIFO
 123          */
 124         while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
 125                 XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
 126                 XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
 127         }
 128
 129         /*
 130          * Clear status register by reading register and
 131          * writing 1 to clear the write to clear bits
 132          */
 133         XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
 134         XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
 135                                 XQSPIPS_IXR_WR_TO_CLR_MASK);
 136
 137         /*
 138          * Write default value to configuration register
 139          */
 140         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
 141                                 XQSPIPS_CR_RESET_STATE);
 142
 143
 144         /*
 145          * De-select linear mode
 146          */
 147         XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
 148                                 0x0);
 149
 150 }
 151
 152 /*****************************************************************************/
 153 /**
 154 *
 155 * Initializes QSPI to Linear mode with default QSPI boot settings.
 156 *
 157 * @param        None
 158 *
 159 * @return       None.
 160 *
 161 * @note         None.
 162 *
 163 ******************************************************************************/
 164 void XQspiPs_LinearInit(u32 BaseAddress)
 165 {
 166         u32 BaudRateDiv;
 167         u32 LinearCfg;
 168
 169         /*
 170          * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
 171          * should be set to 0x001; hence shift the value and use the mask.
 172          */
 173         BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
 174                         XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
 175         /*
 176          * Write configuration register with default values, slave selected &
 177          * pre-scaler value for divide by 4
 178          */
 179         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
 180                                 ((XQSPIPS_CR_RESET_STATE |
 181                                 XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
 182                                 (~XQSPIPS_CR_SSCTRL_MASK) ));
 183
 184         /*
 185          * Write linear configuration register with default value -
 186          * enable linear mode and use fast read.
 187          */
 188
 189         if(XPAR_PS7_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
 190
 191                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
 192
 193         }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
 194                         XQSPIPS_CONNECTION_MODE_STACKED){
 195
 196                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
 197                                 XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
 198
 199         }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
 200                         XQSPIPS_CONNECTION_MODE_PARALLEL){
 201
 202                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
 203                                 XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
 204                                 XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
 205
 206         }
 207
 208         XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
 209                                 LinearCfg);
 210
 211         /*
 212          * Enable device
 213          */
 214         XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
 215                                 XQSPIPS_ER_ENABLE_MASK);
 216
 217 }
 218
 219