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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup qspips_v3_0
39 * Contains low level functions, primarily reset related.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- --- -------- -----------------------------------------------
46 * 2.03a hk 09/17/13 First release
50 ******************************************************************************/
52 /***************************** Include Files *********************************/
54 #include "xqspips_hw.h"
57 /************************** Constant Definitions *****************************/
59 /** @name Pre-scaler value for divided by 4
61 * Pre-scaler value for divided by 4
65 #define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
68 /**************************** Type Definitions *******************************/
70 /***************** Macros (Inline Functions) Definitions *********************/
72 /************************** Function Prototypes ******************************/
74 /************************** Variable Definitions *****************************/
77 /*****************************************************************************/
80 * Resets QSPI by disabling the device and bringing it to reset state through
89 ******************************************************************************/
90 void XQspiPs_ResetHw(u32 BaseAddress)
97 XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
98 XQSPIPS_IXR_DISABLE_ALL);
103 XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
107 * De-assert slave select lines.
109 ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
110 ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
111 XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
114 * Write default value to RX and TX threshold registers
115 * RX threshold should be set to 1 here because the corresponding
116 * status bit is used next to clear the RXFIFO
118 XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
119 (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
120 XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
121 (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
126 while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
127 XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
128 XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
132 * Clear status register by reading register and
133 * writing 1 to clear the write to clear bits
135 XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
136 XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
137 XQSPIPS_IXR_WR_TO_CLR_MASK);
140 * Write default value to configuration register
142 XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
143 XQSPIPS_CR_RESET_STATE);
147 * De-select linear mode
149 XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
154 /*****************************************************************************/
157 * Initializes QSPI to Linear mode with default QSPI boot settings.
165 ******************************************************************************/
166 void XQspiPs_LinearInit(u32 BaseAddress)
172 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
173 * should be set to 0x001; hence shift the value and use the mask.
175 BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
176 XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
178 * Write configuration register with default values, slave selected &
179 * pre-scaler value for divide by 4
181 XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
182 ((XQSPIPS_CR_RESET_STATE |
183 XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
184 (~XQSPIPS_CR_SSCTRL_MASK) ));
187 * Write linear configuration register with default value -
188 * enable linear mode and use fast read.
191 if(XPAR_PS7_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
193 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
195 }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
196 XQSPIPS_CONNECTION_MODE_STACKED){
198 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
199 XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
201 }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
202 XQSPIPS_CONNECTION_MODE_PARALLEL){
204 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
205 XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
206 XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
210 XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
216 XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
217 XQSPIPS_ER_ENABLE_MASK);