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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup qspips_v3_2
39 * Contains low level functions, primarily reset related.
42 * MODIFICATION HISTORY:
44 * Ver Who Date Changes
45 * ----- --- -------- -----------------------------------------------
46 * 2.03a hk 09/17/13 First release
47 * 3.1 hk 06/19/14 When writing to the configuration register, set/reset
48 * required bits leaving reserved bits untouched. CR# 796813.
52 ******************************************************************************/
54 /***************************** Include Files *********************************/
56 #include "xqspips_hw.h"
59 /************************** Constant Definitions *****************************/
61 /** @name Pre-scaler value for divided by 4
63 * Pre-scaler value for divided by 4
67 #define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
70 /**************************** Type Definitions *******************************/
72 /***************** Macros (Inline Functions) Definitions *********************/
74 /************************** Function Prototypes ******************************/
76 /************************** Variable Definitions *****************************/
79 /*****************************************************************************/
82 * Resets QSPI by disabling the device and bringing it to reset state through
91 ******************************************************************************/
92 void XQspiPs_ResetHw(u32 BaseAddress)
99 XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
100 XQSPIPS_IXR_DISABLE_ALL);
105 XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
109 * De-assert slave select lines.
111 ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
112 ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
113 XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
116 * Write default value to RX and TX threshold registers
117 * RX threshold should be set to 1 here because the corresponding
118 * status bit is used next to clear the RXFIFO
120 XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
121 (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
122 XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
123 (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
128 while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
129 XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
130 XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
134 * Clear status register by reading register and
135 * writing 1 to clear the write to clear bits
137 XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
138 XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
139 XQSPIPS_IXR_WR_TO_CLR_MASK);
142 * Write default value to configuration register
144 ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
145 ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
146 ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
147 XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
150 * De-select linear mode
152 XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
157 /*****************************************************************************/
160 * Initializes QSPI to Linear mode with default QSPI boot settings.
168 ******************************************************************************/
169 void XQspiPs_LinearInit(u32 BaseAddress)
176 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
177 * should be set to 0x001; hence shift the value and use the mask.
179 BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
180 XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
182 * Write configuration register with default values, slave selected &
183 * pre-scaler value for divide by 4
185 ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
186 ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
187 ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
188 XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
191 * Write linear configuration register with default value -
192 * enable linear mode and use fast read.
195 if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
197 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
199 }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
200 XQSPIPS_CONNECTION_MODE_STACKED){
202 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
203 XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
205 }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
206 XQSPIPS_CONNECTION_MODE_PARALLEL){
208 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
209 XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
210 XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
214 XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
220 XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
221 XQSPIPS_ER_ENABLE_MASK);