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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup scugic_v3_8
39 * This header file contains identifiers and HW access functions (or
40 * macros) that can be used to access the device. The user should refer to the
41 * hardware device specification for more details of the device operation.
42 * The driver functions/APIs are defined in xscugic.h.
44 * This GIC device has two parts, a distributor and CPU interface(s). Each part
45 * has separate register definition sections.
49 * MODIFICATION HISTORY:
51 * Ver Who Date Changes
52 * ----- ---- -------- -----------------------------------------------------
53 * 1.00a drg 01/19/10 First release
54 * 1.01a sdm 11/09/11 "xil_exception.h" added as include.
55 * Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
56 * added to enable or disable interrupts based on
57 * Distributor Register base address. Normally users use
58 * XScuGic instance and call XScuGic_Enable or
59 * XScuGic_Disable to enable/disable interrupts. These
60 * new macros are provided when user does not want to
61 * use an instance pointer but still wants to enable or
63 * Function prototypes for functions (present in newly
64 * added file xscugic_hw.c) are added.
65 * 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
67 * 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
68 * XScuGic_SetPriTrigTypeByDistAddr and
69 * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
70 * 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
72 * 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
73 * 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
74 * for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
75 * 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
76 * and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
77 * API's can be used by applications to unmap specific/all
78 * interrupts from target CPU. It fixes CR#992490.
81 ******************************************************************************/
83 #ifndef XSCUGIC_HW_H /* prevent circular inclusions */
84 #define XSCUGIC_HW_H /* by using protection macros */
90 /***************************** Include Files *********************************/
92 #include "xil_types.h"
93 #include "xil_assert.h"
95 #include "xil_exception.h"
97 /************************** Constant Definitions *****************************/
100 * The maximum number of interrupts supported by the hardware.
103 #define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
105 #define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
109 * The maximum priority value that can be used in the GIC.
111 #define XSCUGIC_MAX_INTR_PRIO_VAL 248U
112 #define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
114 /** @name Distributor Interface Register Map
116 * Define the offsets from the base address for all Distributor registers of
117 * the interrupt controller, some registers may be reserved in the hardware
121 #define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
123 #define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
125 #define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
127 #define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
129 #define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
131 #define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
132 #define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
134 #define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
136 #define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
137 #define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
138 #define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
139 Register 0x800-0x8FB */
140 #define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
141 Register 0xC00-0xCFC */
142 #define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
143 #define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
145 #define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
147 #define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
148 Interrupt Register */
149 #define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
150 #define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
153 /** @name Distributor Enable Register
154 * Controls if the distributor response to external interrupt inputs.
157 #define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
160 /** @name Interrupt Controller Type Register
163 #define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
166 #define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
167 #define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
168 #define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
171 /** @name Implementor ID Register
172 * Implementor and revision information.
175 #define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
176 #define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
179 /** @name Interrupt Security Registers
180 * Each bit controls the security level of an interrupt, either secure or non
181 * secure. These registers can only be accessed using secure read and write.
182 * There are registers for each of the CPU interfaces at offset 0x080. A
183 * register set for the SPI interrupts is available to all CPU interfaces.
184 * There are up to 32 of these registers staring at location 0x084.
187 #define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
191 /** @name Enable Set Register
192 * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
193 * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
195 * There are registers for each of the CPU interfaces at offset 0x100. With up
196 * to 8 registers aliased to the same address. A register set for the SPI
197 * interrupts is available to all CPU interfaces.
198 * There are up to 32 of these registers staring at location 0x104.
201 #define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
205 /** @name Enable Clear Register
206 * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
207 * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
208 * sets the corresponding bit to 0.
209 * There are registers for each of the CPU interfaces at offset 0x180. With up
210 * to 8 registers aliased to the same address.
211 * A register set for the SPI interrupts is available to all CPU interfaces.
212 * There are up to 32 of these registers staring at location 0x184.
215 #define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
219 /** @name Pending Set Register
220 * Each bit controls the Pending or Active and Pending state of an interrupt, a
221 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
222 * an interrupt to the pending state.
223 * There are registers for each of the CPU interfaces at offset 0x200. With up
224 * to 8 registers aliased to the same address.
225 * A register set for the SPI interrupts is available to all CPU interfaces.
226 * There are up to 32 of these registers staring at location 0x204.
229 #define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
233 /** @name Pending Clear Register
234 * Each bit can clear the Pending or Active and Pending state of an interrupt, a
235 * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
236 * clears the pending state of an interrupt.
237 * There are registers for each of the CPU interfaces at offset 0x280. With up
238 * to 8 registers aliased to the same address.
239 * A register set for the SPI interrupts is available to all CPU interfaces.
240 * There are up to 32 of these registers staring at location 0x284.
243 #define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
247 /** @name Active Status Register
248 * Each bit provides the Active status of an interrupt, a
249 * 0 is not Active, a 1 is Active. This is a read only register.
250 * There are registers for each of the CPU interfaces at offset 0x300. With up
251 * to 8 registers aliased to each address.
252 * A register set for the SPI interrupts is available to all CPU interfaces.
253 * There are up to 32 of these registers staring at location 0x380.
256 #define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
260 /** @name Priority Level Register
261 * Each byte in a Priority Level Register sets the priority level of an
262 * interrupt. Reading the register provides the priority level of an interrupt.
263 * There are registers for each of the CPU interfaces at offset 0x400 through
264 * 0x41C. With up to 8 registers aliased to each address.
265 * 0 is highest priority, 0xFF is lowest.
266 * A register set for the SPI interrupts is available to all CPU interfaces.
267 * There are up to 255 of these registers staring at location 0x420.
270 #define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
272 #define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
273 actually the lowest priority*/
276 /** @name SPI Target Register 0x800-0x8FB
277 * Each byte references a separate SPI and programs which of the up to 8 CPU
278 * interfaces are sent a Pending interrupt.
279 * There are registers for each of the CPU interfaces at offset 0x800 through
280 * 0x81C. With up to 8 registers aliased to each address.
281 * A register set for the SPI interrupts is available to all CPU interfaces.
282 * There are up to 255 of these registers staring at location 0x820.
284 * This driver does not support multiple CPU interfaces. These are included
285 * for complete documentation.
288 #define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
289 #define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
290 #define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
291 #define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
292 #define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
293 #define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
294 #define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
295 #define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
298 /** @name Interrupt Configuration Register 0xC00-0xCFC
299 * The interrupt configuration registers program an SFI to be active HIGH level
300 * sensitive or rising edge sensitive.
301 * Each bit pair describes the configuration for an INT_ID.
302 * SFI Read Only b10 always
303 * PPI Read Only depending on how the PPIs are configured.
304 * b01 Active HIGH level sensitive
305 * b11 Rising edge sensitive
306 * SPI LSB is read only.
307 * b01 Active HIGH level sensitive
308 * b11 Rising edge sensitive/
309 * There are registers for each of the CPU interfaces at offset 0xC00 through
310 * 0xC04. With up to 8 registers aliased to each address.
311 * A register set for the SPI interrupts is available to all CPU interfaces.
312 * There are up to 255 of these registers staring at location 0xC08.
315 #define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
318 /** @name PPI Status Register
319 * Enables an external AMBA master to access the status of the PPI inputs.
320 * A CPU can only read the status of its local PPI signals and cannot read the
321 * status for other CPUs.
322 * This register is aliased for each CPU interface.
325 #define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
326 #define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
327 #define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
328 #define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
329 #define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
330 #define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
331 #define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
332 #define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
333 #define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
334 #define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
335 #define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
336 #define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
337 #define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
338 #define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
339 #define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
340 #define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
343 /** @name SPI Status Register 0xd04-0xd7C
344 * Enables an external AMBA master to access the status of the SPI inputs.
345 * There are up to 63 registers if the maximum number of SPI inputs are
349 #define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
353 /** @name AHB Configuration Register
354 * Provides the status of the CFGBIGEND input signal and allows the endianess
355 * of the GIC to be set.
358 #define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
359 1-GIC uses Big Endian */
360 #define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
361 1-use the AHB_END bit */
362 #define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
366 /** @name Software Triggered Interrupt Register
367 * Controls issueing of software interrupts.
370 #define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
371 #define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
372 b00-Use the target List
373 b01-All CPUs except requester
376 #define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
377 #define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
378 #define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
379 signaled to the CPU*/
382 /** @name CPU Interface Register Map
384 * Define the offsets from the base address for all CPU registers of the
385 * interrupt controller, some registers may be reserved in the hardware device.
388 #define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
390 #define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
391 #define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
392 #define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
393 #define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
394 #define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
395 #define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
397 #define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
398 Binary Point Register */
400 /**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
405 /** @name Control Register
406 * CPU Interface Control register definitions
407 * All bits are defined here although some are not available in the non-secure
411 #define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
412 0=separate registers,
413 1=both use bin_pt_s */
414 #define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
417 1=Use FIQ for secure, IRQ for non*/
418 #define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
419 #define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
420 #define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
423 /** @name Priority Mask Register
424 * Priority Mask register definitions
425 * The CPU interface does not send interrupt if the level of the interrupt is
426 * lower than the level of the register.
429 /*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
432 /** @name Binary Point Register
433 * Binary Point register definitions
437 #define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
438 Value Secure Non-secure
450 /** @name Interrupt Acknowledge Register
451 * Interrupt Acknowledge register definitions
452 * Identifies the current Pending interrupt, and the CPU ID for software
455 #define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
456 #define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
459 /** @name End of Interrupt Register
460 * End of Interrupt register definitions
461 * Allows the CPU to signal the GIC when it completes an interrupt service
464 #define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
468 /** @name Running Priority Register
469 * Running Priority register definitions
470 * Identifies the interrupt priority level of the highest priority active
473 #define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
477 * Highest Pending Interrupt register definitions
478 * Identifies the interrupt priority of the highest priority pending interupt
480 #define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
481 /*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
484 /***************** Macros (Inline Functions) Definitions *********************/
486 /****************************************************************************/
489 * Read the Interrupt Configuration Register offset for an interrupt id.
491 * @param InterruptID is the interrupt number.
493 * @return The 32-bit value of the offset
497 *****************************************************************************/
498 #define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
499 ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
501 /****************************************************************************/
504 * Read the Interrupt Priority Register offset for an interrupt id.
506 * @param InterruptID is the interrupt number.
508 * @return The 32-bit value of the offset
512 *****************************************************************************/
513 #define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
514 ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
516 /****************************************************************************/
519 * Read the SPI Target Register offset for an interrupt id.
521 * @param InterruptID is the interrupt number.
523 * @return The 32-bit value of the offset
527 *****************************************************************************/
528 #define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
529 ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
531 /****************************************************************************/
534 * Read the Interrupt Clear-Enable Register offset for an interrupt ID
536 * @param Register is the register offset for the clear/enable bank.
537 * @param InterruptID is the interrupt number.
539 * @return The 32-bit value of the offset
543 *****************************************************************************/
544 #define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
545 ((Register) + (((InterruptID)/32U) * 4U))
547 /****************************************************************************/
550 * Read the given Intc register.
552 * @param BaseAddress is the base address of the device.
553 * @param RegOffset is the register offset to be read
555 * @return The 32-bit value of the register
559 * u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
561 *****************************************************************************/
562 #define XScuGic_ReadReg(BaseAddress, RegOffset) \
563 (Xil_In32((BaseAddress) + (RegOffset)))
566 /****************************************************************************/
569 * Write the given Intc register.
571 * @param BaseAddress is the base address of the device.
572 * @param RegOffset is the register offset to be written
573 * @param Data is the 32-bit value to write to the register
579 * void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
581 *****************************************************************************/
582 #define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
583 (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
586 /****************************************************************************/
589 * Enable specific interrupt(s) in the interrupt controller.
591 * @param DistBaseAddress is the Distributor Register base address of the
593 * @param Int_Id is the ID of the interrupt source and should be in the
594 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
598 * @note C-style signature:
599 * void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
601 *****************************************************************************/
602 #define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
603 XScuGic_WriteReg((DistBaseAddress), \
604 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
605 (0x00000001U << ((Int_Id) % 32U)))
607 /****************************************************************************/
610 * Disable specific interrupt(s) in the interrupt controller.
612 * @param DistBaseAddress is the Distributor Register base address of the
614 * @param Int_Id is the ID of the interrupt source and should be in the
615 * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
620 * @note C-style signature:
621 * void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
623 *****************************************************************************/
624 #define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
625 XScuGic_WriteReg((DistBaseAddress), \
626 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
627 (0x00000001U << ((Int_Id) % 32U)))
630 /************************** Function Prototypes ******************************/
632 void XScuGic_DeviceInterruptHandler(void *DeviceId);
633 s32 XScuGic_DeviceInitialize(u32 DeviceId);
634 void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
635 Xil_InterruptHandler Handler, void *CallBackRef);
636 void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
637 u8 Priority, u8 Trigger);
638 void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
639 u8 *Priority, u8 *Trigger);
640 void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
641 u8 Cpu_Id, u32 Int_Id);
642 void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
644 /************************** Variable Definitions *****************************/
649 #endif /* end of protection macro */