1 /******************************************************************************
3 * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * Use of the Software is limited solely to applications:
16 * (a) running on a Xilinx device, or
17 * (b) that interact with a Xilinx device through a bus or interconnect.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27 * Except as contained in this notice, the name of the Xilinx shall not be used
28 * in advertising or otherwise to promote the sale, use or other dealings in
29 * this Software without prior written authorization from Xilinx.
31 ******************************************************************************/
32 /****************************************************************************/
36 * @addtogroup scuwdt_v2_0
39 * This file contains the hardware interface to the Xilinx SCU private Watch Dog
43 * MODIFICATION HISTORY:
45 * Ver Who Date Changes
46 * ----- --- -------- ---------------------------------------------
47 * 1.00a sdm 01/15/10 First release
48 * 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
49 * of 0x20 as the base address obtained from the tools
51 * 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
52 * when the xstatus.h in the common driver overwrites
53 * the xstatus.h of the standalone BSP during the
57 ******************************************************************************/
58 #ifndef XSCUWDT_HW_H /* prevent circular inclusions */
59 #define XSCUWDT_HW_H /* by using protection macros */
65 /***************************** Include Files *********************************/
67 #include "xil_types.h"
69 #include "xil_assert.h"
70 /************************** Constant Definitions *****************************/
72 /** @name Register Map
73 * Offsets of registers from the start of the device. The WDT registers start at
78 #define XSCUWDT_LOAD_OFFSET 0x00 /**< Watchdog Load Register */
79 #define XSCUWDT_COUNTER_OFFSET 0x04 /**< Watchdog Counter Register */
80 #define XSCUWDT_CONTROL_OFFSET 0x08 /**< Watchdog Control Register */
81 #define XSCUWDT_ISR_OFFSET 0x0C /**< Watchdog Interrupt Status Register */
82 #define XSCUWDT_RST_STS_OFFSET 0x10 /**< Watchdog Reset Status Register */
83 #define XSCUWDT_DISABLE_OFFSET 0x14 /**< Watchdog Disable Register */
86 /** @name Watchdog Control register
87 * This register bits control the prescaler, WD/Timer mode, Intr enable,
88 * auto-reload, watchdog enable.
92 #define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */
93 #define XSCUWDT_CONTROL_PRESCALER_SHIFT 8
94 #define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008 /**< Watchdog/Timer mode */
95 #define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004 /**< Intr enable (in
97 #define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in
99 #define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001 /**< Watchdog enable */
102 /** @name Interrupt Status register
103 * This register indicates the Counter register has reached zero in Counter
108 #define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */
111 /** @name Reset Status register
112 * This register indicates the Counter register has reached zero in Watchdog
113 * mode and a reset request is sent.
117 #define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001 /**< Time out occured */
120 /** @name Disable register
121 * This register is used to switch from watchdog mode to timer mode.
122 * The software must write 0x12345678 and 0x87654321 successively to the
123 * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
124 * Control Register is set to zero.
127 #define XSCUWDT_DISABLE_VALUE1 0x12345678 /**< Watchdog mode disable
129 #define XSCUWDT_DISABLE_VALUE2 0x87654321 /**< Watchdog mode disable
133 /**************************** Type Definitions *******************************/
135 /***************** Macros (Inline Functions) Definitions *********************/
137 /****************************************************************************/
140 * Read the given register.
142 * @param BaseAddr is the base address of the device
143 * @param RegOffset is the register offset to be read
145 * @return The 32-bit value of the register
147 * @note C-style signature:
148 * u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
150 *****************************************************************************/
151 #define XScuWdt_ReadReg(BaseAddr, RegOffset) \
152 Xil_In32((BaseAddr) + (RegOffset))
154 /****************************************************************************/
157 * Write the given register.
159 * @param BaseAddr is the base address of the device
160 * @param RegOffset is the register offset to be written
161 * @param Data is the 32-bit value to write to the register
165 * @note C-style signature:
166 * void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
168 *****************************************************************************/
169 #define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
170 Xil_Out32((BaseAddr) + (RegOffset), (Data))
172 /************************** Function Prototypes ******************************/
174 /************************** Variable Definitions *****************************/
180 #endif /* end of protection macro */