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31 ******************************************************************************
33 * _program_timer_hw.h:
34 * Timer related functions
36 ******************************************************************************/
38 #ifndef PROFILE_TIMER_HW_H
39 #define PROFILE_TIMER_HW_H
45 # define SYNCHRONIZE_IO __asm__ volatile ("eieio")
47 # define SYNCHRONIZE_IO __asm volatile(" eieio")
49 # define SYNCHRONIZE_IO
54 #define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
55 #define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
57 #define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
58 #define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
61 #define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
62 ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
63 (u32)(RegOffset)), (u32)(ValueToWrite))
65 #define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
66 ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
68 #define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
69 ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
72 #define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
73 ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
82 #include "xexception_l.h"
84 #include "xpseudo_asm.h"
87 #ifdef TIMER_CONNECT_INTC
90 #endif /* TIMER_CONNECT_INTC */
92 #if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
93 #include "xtmrctr_l.h"
97 #include "xscutimer_hw.h"
101 extern u32 timer_clk_ticks ;
103 /*--------------------------------------------------------------------
104 * PowerPC Target - Timer related functions
105 *-------------------------------------------------------------------- */
108 #ifdef PPC_PIT_INTERRUPT
109 u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
113 #define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
114 #define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
115 #define XREG_SPR_PIT XREG_SPR_DEC
116 #define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
119 /* --------------------------------------------------------------------
120 * Disable the Timer - During Profiling
123 * 1. XTime_PITDisableInterrupt() ;
124 * 2. Store the remaining timer clk tick
125 * 3. Stop the PIT Timer
126 *-------------------------------------------------------------------- */
128 #ifdef PPC_PIT_INTERRUPT
129 #define disable_timer() \
132 val=mfspr(XREG_SPR_TCR); \
133 mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
134 timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
135 mtspr(XREG_SPR_PIT, 0); \
138 #define disable_timer() \
140 u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
141 u32 tmp_v = ProfIo_In32(addr); \
142 tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
143 ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
149 /* --------------------------------------------------------------------
153 * 1. Load the remaining timer clk ticks
154 * 2. XTime_PITEnableInterrupt() ;
155 *-------------------------------------------------------------------- */
156 #ifdef PPC_PIT_INTERRUPT
157 #define enable_timer() \
160 val=mfspr(XREG_SPR_TCR); \
161 mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
162 mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
165 #define enable_timer() \
167 u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
168 u32 tmp_v = ProfIo_In32(addr); \
169 tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
170 ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
176 /* --------------------------------------------------------------------
177 * Send Ack to Timer Interrupt
180 * 1. Load the timer clk ticks
181 * 2. Enable AutoReload and Interrupt
182 * 3. Clear PIT Timer Status bits
183 *-------------------------------------------------------------------- */
184 #ifdef PPC_PIT_INTERRUPT
185 #define timer_ack() \
188 mtspr(XREG_SPR_PIT, timer_clk_ticks); \
189 mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
190 val=mfspr(XREG_SPR_TCR); \
191 mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
194 #define timer_ack() \
197 csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
198 ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
202 /*-------------------------------------------------------------------- */
203 #endif /* PROC_PPC */
204 /* -------------------------------------------------------------------- */
209 /* --------------------------------------------------------------------
210 * MicroBlaze Target - Timer related functions
211 *-------------------------------------------------------------------- */
212 #ifdef PROC_MICROBLAZE
214 /* --------------------------------------------------------------------
215 * Disable the Timer during Call-Graph Data collection
217 *-------------------------------------------------------------------- */
218 #define disable_timer() \
220 u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
221 Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
222 Addr += (u32)XTC_TCSR_OFFSET; \
223 u32 tmp_v = ProfIo_In32(Addr); \
224 tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
225 u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
226 OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
227 OutAddr += (u32)XTC_TCSR_OFFSET; \
228 ProfIo_Out32(OutAddr, (u32)tmp_v); \
232 /* --------------------------------------------------------------------
233 * Enable the Timer after Call-Graph Data collection
235 *-------------------------------------------------------------------- */
236 #define enable_timer() \
238 u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
239 Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
240 Addr += (u32)XTC_TCSR_OFFSET; \
241 u32 tmp_v = (u32)ProfIo_In32(Addr); \
242 tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
243 ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
247 /* --------------------------------------------------------------------
248 * Send Ack to Timer Interrupt
250 *-------------------------------------------------------------------- */
251 #define timer_ack() \
254 csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
255 ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
258 /*-------------------------------------------------------------------- */
259 #endif /* PROC_MICROBLAZE */
260 /*-------------------------------------------------------------------- */
262 /* --------------------------------------------------------------------
263 * Cortex A9 Target - Timer related functions
264 *-------------------------------------------------------------------- */
267 /* --------------------------------------------------------------------
268 * Disable the Timer during Call-Graph Data collection
270 *-------------------------------------------------------------------- */
271 #define disable_timer() \
274 Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
275 Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
276 Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
280 /* --------------------------------------------------------------------
281 * Enable the Timer after Call-Graph Data collection
283 *-------------------------------------------------------------------- */
284 #define enable_timer() \
287 Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
288 Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
289 Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
293 /* --------------------------------------------------------------------
294 * Send Ack to Timer Interrupt
296 *-------------------------------------------------------------------- */
297 #define timer_ack() \
299 Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
300 (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
303 /*-------------------------------------------------------------------- */
304 #endif /* PROC_CORTEXA9 */
305 /*-------------------------------------------------------------------- */