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32 /*****************************************************************************/
34 * @file translation_table.s
36 * This file contains the initialization for the MMU table in RAM
37 * needed by the Cortex A9 processor
40 * MODIFICATION HISTORY:
42 * Ver Who Date Changes
43 * ----- ---- -------- ---------------------------------------------------
44 * 1.00a ecm 10/20/09 Initial version
45 * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
46 * 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
47 * instead of strongly-ordered.
48 * 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
49 * 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
50 * and 0xe0000000 - 0xe1ffffff is broken down into
51 * 0xe0000000 - 0xe02fffff (memory mapped devides)
52 * 0xe0300000 - 0xe0ffffff (reserved) and
53 * 0xe1000000 - 0xe1ffffff (NAND)
54 * 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
55 * if DDR is present or not and accordingly generate the
63 ******************************************************************************/
64 #include "xparameters.h"
70 /* Each table entry occupies one 32-bit word and there are
71 * 4096 entries, so the entire table takes up 16KB.
72 * Each entry covers a 1MB section.
76 #ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
77 .set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
78 .set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
79 .set DDR_SIZE, (DDR_END - DDR_START)+1
80 .set DDR_REG, DDR_SIZE/0x100000
85 .set UNDEF_REG, 0x3FF - DDR_REG
87 /*0x00000000 - 0x00100000 (cacheable )*/
88 .word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
89 .set SECT, SECT+0x100000
91 .rept DDR_REG /* (DDR Cacheable) */
92 .word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
93 .set SECT, SECT+0x100000
96 .rept UNDEF_REG /* (unassigned/reserved).
97 * Generates a translation fault if accessed */
98 .word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
99 .set SECT, SECT+0x100000
103 .rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
104 .word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
105 .set SECT, SECT+0x100000
108 .rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
109 .word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
110 .set SECT, SECT+0x100000
113 .rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
114 * Generates a translation fault if accessed */
115 .word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
116 .set SECT, SECT+0x100000
119 .rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
120 * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
121 .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
122 .set SECT, SECT+0x100000
125 .rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
126 * Generates a translation fault if accessed */
127 .word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
128 .set SECT, SECT+0x100000
131 .rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
132 .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
133 .set SECT, SECT+0x100000
136 .rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
137 .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
138 .set SECT, SECT+0x100000
141 .rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
142 .word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
143 .set SECT, SECT+0x100000
146 .rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
147 * Generates a translation fault if accessed */
148 .word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
149 .set SECT, SECT+0x100000
152 /* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
153 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
154 1MB, it is not possible to define separate regions for them */
156 .rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
158 .word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
159 .set SECT, SECT+0x100000
162 .rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
163 * Generates a translation fault if accessed */
164 .word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
165 .set SECT, SECT+0x100000
168 .rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
169 .word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
170 .set SECT, SECT+0x100000
173 .rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
174 * Generates a translation fault if accessed */
175 .word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
176 .set SECT, SECT+0x100000
179 /* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
180 1MB, it is not possible to define separate region for it
182 /* 0xfff00000 - 0xffffffff
183 256K OCM when mapped to high address space
185 .word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
186 .set SECT, SECT+0x100000