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32 /*****************************************************************************/
35 * @file xil_exception.h
37 * This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
38 * For exception related functions that can be used across all Xilinx supported
39 * processors, please use xil_exception.h.
41 * @addtogroup arm_exception_apis ARM Processor Exception Handling
43 * ARM processors specific exception related APIs for cortex A53,A9 and R5 can
44 * utilized for enabling/disabling IRQ, registering/removing handler for
45 * exceptions or initializing exception vector table with null handler.
48 * MODIFICATION HISTORY:
50 * Ver Who Date Changes
51 * ----- -------- -------- -----------------------------------------------
52 * 5.2 pkp 28/05/15 First release
53 * 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
56 ******************************************************************************/
58 #ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
59 #define XIL_EXCEPTION_H /* by using protection macros */
61 /***************************** Include Files ********************************/
63 #include "xil_types.h"
64 #include "xpseudo_asm.h"
70 /************************** Constant Definitions ****************************/
72 #define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
73 #define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
74 #define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
76 #define XIL_EXCEPTION_ID_FIRST 0U
77 #if defined (__aarch64__)
78 #define XIL_EXCEPTION_ID_SYNC_INT 1U
79 #define XIL_EXCEPTION_ID_IRQ_INT 2U
80 #define XIL_EXCEPTION_ID_FIQ_INT 3U
81 #define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
82 #define XIL_EXCEPTION_ID_LAST 5U
84 #define XIL_EXCEPTION_ID_RESET 0U
85 #define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
86 #define XIL_EXCEPTION_ID_SWI_INT 2U
87 #define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
88 #define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
89 #define XIL_EXCEPTION_ID_IRQ_INT 5U
90 #define XIL_EXCEPTION_ID_FIQ_INT 6U
91 #define XIL_EXCEPTION_ID_LAST 6U
95 * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
97 #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
99 /**************************** Type Definitions ******************************/
102 * This typedef is the exception handler function.
104 typedef void (*Xil_ExceptionHandler)(void *data);
105 typedef void (*Xil_InterruptHandler)(void *data);
107 /***************** Macros (Inline Functions) Definitions ********************/
109 /****************************************************************************/
111 * @brief Enable Exceptions.
113 * @param Mask: Value for enabling the exceptions.
117 * @note If bit is 0, exception is enabled.
118 * C-Style signature: void Xil_ExceptionEnableMask(Mask)
120 ******************************************************************************/
121 #if defined (__GNUC__) || defined (__ICCARM__)
122 #define Xil_ExceptionEnableMask(Mask) \
123 mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
125 #define Xil_ExceptionEnableMask(Mask) \
127 register u32 Reg __asm("cpsr"); \
128 mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
131 /****************************************************************************/
133 * @brief Enable the IRQ exception.
139 ******************************************************************************/
140 #define Xil_ExceptionEnable() \
141 Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
143 /****************************************************************************/
145 * @brief Disable Exceptions.
147 * @param Mask: Value for disabling the exceptions.
151 * @note If bit is 1, exception is disabled.
152 * C-Style signature: Xil_ExceptionDisableMask(Mask)
154 ******************************************************************************/
155 #if defined (__GNUC__) || defined (__ICCARM__)
156 #define Xil_ExceptionDisableMask(Mask) \
157 mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
159 #define Xil_ExceptionDisableMask(Mask) \
161 register u32 Reg __asm("cpsr"); \
162 mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
165 /****************************************************************************/
167 * Disable the IRQ exception.
173 ******************************************************************************/
174 #define Xil_ExceptionDisable() \
175 Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
177 #if !defined (__aarch64__) && !defined (ARMA53_32)
178 /****************************************************************************/
180 * @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
181 * API is defined for cortex-a9 and cortex-r5.
185 * @note This macro is supposed to be used from interrupt handlers. In the
186 * interrupt handler the interrupts are disabled by default (I and F
187 * are 1). To allow nesting of interrupts, this macro should be
188 * used. It clears the I and F bits by changing the ARM mode to
189 * system mode. Once these bits are cleared and provided the
190 * preemption of interrupt conditions are met in the GIC, nesting of
191 * interrupts will start happening.
192 * Caution: This macro must be used with caution. Before calling this
193 * macro, the user must ensure that the source of the current IRQ
194 * is appropriately cleared. Otherwise, as soon as we clear the I and
195 * F bits, there can be an infinite loop of interrupts with an
196 * eventual crash (all the stack space getting consumed).
197 ******************************************************************************/
198 #define Xil_EnableNestedInterrupts() \
199 __asm__ __volatile__ ("stmfd sp!, {lr}"); \
200 __asm__ __volatile__ ("mrs lr, spsr"); \
201 __asm__ __volatile__ ("stmfd sp!, {lr}"); \
202 __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
203 __asm__ __volatile__ ("stmfd sp!, {lr}");
205 /****************************************************************************/
207 * @brief Disable the nested interrupts by setting the I and F bits. This API
208 * is defined for cortex-a9 and cortex-r5.
212 * @note This macro is meant to be called in the interrupt service routines.
213 * This macro cannot be used independently. It can only be used when
214 * nesting of interrupts have been enabled by using the macro
215 * Xil_EnableNestedInterrupts(). In a typical flow, the user first
216 * calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
217 * point. The user then must call this macro before exiting the interrupt
218 * service routine. This macro puts the ARM back in IRQ/FIQ mode and
219 * hence sets back the I and F bits.
220 ******************************************************************************/
221 #define Xil_DisableNestedInterrupts() \
222 __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
223 __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
224 __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
225 __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
226 __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
229 /************************** Variable Definitions ****************************/
231 /************************** Function Prototypes *****************************/
233 extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
234 Xil_ExceptionHandler Handler,
237 extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
239 extern void Xil_ExceptionInit(void);
240 #if defined (__aarch64__)
241 void Xil_SyncAbortHandler(void *CallBackRef);
242 void Xil_SErrorAbortHandler(void *CallBackRef);
244 extern void Xil_DataAbortHandler(void *CallBackRef);
245 extern void Xil_PrefetchAbortHandler(void *CallBackRef);
246 extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
251 #endif /* __cplusplus */
253 #endif /* XIL_EXCEPTION_H */
255 * @} End of "addtogroup arm_exception_apis".