git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.c

   1 /******************************************************************************
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  13 * all copies or substantial portions of the Software.
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  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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  29 * this Software without prior written authorization from Xilinx.
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  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xil_testcache.c
  36 *
  37 * Contains utility functions to test cache.
  38 *
  39 * <pre>
  40 * MODIFICATION HISTORY:
  41 *
  42 * Ver   Who  Date        Changes
  43 * ----- ---- -------- -------------------------------------------------------
  44 * 1.00a hbm  07/28/09 Initial release
  45 * 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
  46 *                                     cache line.
  47 * </pre>
  48 *
  49 * @note
  50 * This file contain functions that all operate on HAL.
  51 *
  52 ******************************************************************************/
  53 #ifdef __ARM__
  54 #include "xil_cache.h"
  55 #include "xil_testcache.h"
  56 #include "xil_types.h"
  57 #include "xpseudo_asm.h"
  58 #ifdef __aarch64__
  59 #include "xreg_cortexa53.h"
  60 #else
  61 #include "xreg_cortexr5.h"
  62 #endif
  63
  64 #include "xil_types.h"
  65
  66 extern void xil_printf(const char8 *ctrl1, ...);
  67
  68 #define DATA_LENGTH 128
  69
  70 #ifdef __aarch64__
  71 static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
  72 #else
  73 static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
  74 #endif
  75
  76
  77 /*****************************************************************************/
  78 /**
  79 *
  80 * @brief    Perform DCache range related API test such as Xil_DCacheFlushRange
  81 *           and Xil_DCacheInvalidateRange. This test function writes a constant
  82 *           value to the Data array, flushes the range, writes a new value, then
  83 *           invalidates the corresponding range.
  84 * @param        None
  85 *
  86 * @return
  87 *      - -1 is returned for a failure
  88 *      - 0 is returned for a pass
  89 *
  90 *****************************************************************************/
  91 s32 Xil_TestDCacheRange(void)
  92 {
  93         s32 Index;
  94         s32 Status = 0;
  95         u32 CtrlReg;
  96         INTPTR Value;
  97
  98         xil_printf("-- Cache Range Test --\n\r");
  99
 100         for (Index = 0; Index < DATA_LENGTH; Index++)
 101                 Data[Index] = 0xA0A00505;
 102
 103         xil_printf("    initialize Data done:\r\n");
 104
 105         Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
 106
 107         xil_printf("    flush range done\r\n");
 108
 109         dsb();
 110         #ifdef __aarch64__
 111                         CtrlReg = mfcp(SCTLR_EL3);
 112                         CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
 113                         mtcp(SCTLR_EL3,CtrlReg);
 114         #else
 115                         CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 116                         CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
 117                         mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 118         #endif
 119         dsb();
 120
 121         Status = 0;
 122
 123         for (Index = 0; Index < DATA_LENGTH; Index++) {
 124                 Value = Data[Index];
 125                 if (Value != 0xA0A00505) {
 126                         Status = -1;
 127                         xil_printf("Data[%d] = %x\r\n", Index, Value);
 128                         break;
 129                 }
 130         }
 131
 132         if (!Status) {
 133                 xil_printf("    Flush worked\r\n");
 134         }
 135         else {
 136                 xil_printf("Error: flush dcache range not working\r\n");
 137         }
 138         dsb();
 139         #ifdef __aarch64__
 140                         CtrlReg = mfcp(SCTLR_EL3);
 141                         CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
 142                         mtcp(SCTLR_EL3,CtrlReg);
 143                 #else
 144                         CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 145                         CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
 146                         mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 147                 #endif
 148         dsb();
 149         for (Index = 0; Index < DATA_LENGTH; Index++)
 150                 Data[Index] = 0xA0A0C505;
 151
 152
 153
 154         Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
 155
 156         for (Index = 0; Index < DATA_LENGTH; Index++)
 157                 Data[Index] = Index + 3;
 158
 159         Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
 160
 161         xil_printf("    invalidate dcache range done\r\n");
 162         dsb();
 163         #ifdef __aarch64__
 164                         CtrlReg = mfcp(SCTLR_EL3);
 165                         CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
 166                         mtcp(SCTLR_EL3,CtrlReg);
 167         #else
 168                         CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 169                         CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
 170                         mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 171         #endif
 172         dsb();
 173         for (Index = 0; Index < DATA_LENGTH; Index++)
 174                 Data[Index] = 0xA0A0A05;
 175         dsb();
 176         #ifdef __aarch64__
 177                         CtrlReg = mfcp(SCTLR_EL3);
 178                         CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
 179                         mtcp(SCTLR_EL3,CtrlReg);
 180         #else
 181                         CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 182                         CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
 183                         mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 184         #endif
 185         dsb();
 186
 187         Status = 0;
 188
 189         for (Index = 0; Index < DATA_LENGTH; Index++) {
 190                 Value = Data[Index];
 191                 if (Value != 0xA0A0A05) {
 192                         Status = -1;
 193                         xil_printf("Data[%d] = %x\r\n", Index, Value);
 194                         break;
 195                 }
 196         }
 197
 198
 199         if (!Status) {
 200                 xil_printf("    Invalidate worked\r\n");
 201         }
 202         else {
 203                 xil_printf("Error: Invalidate dcache range not working\r\n");
 204         }
 205         xil_printf("-- Cache Range Test Complete --\r\n");
 206         return Status;
 207
 208 }
 209
 210 /*****************************************************************************/
 211 /**
 212 * @brief    Perform DCache all related API test such as Xil_DCacheFlush and
 213 *           Xil_DCacheInvalidate. This test function writes a constant value
 214 *           to the Data array, flushes the DCache, writes a new value,
 215 *           then invalidates the DCache.
 216 *
 217 * @return
 218 *          - 0 is returned for a pass
 219 *          - -1 is returned for a failure
 220 *****************************************************************************/
 221 s32 Xil_TestDCacheAll(void)
 222 {
 223         s32 Index;
 224         s32 Status;
 225         INTPTR Value;
 226         u32 CtrlReg;
 227
 228         xil_printf("-- Cache All Test --\n\r");
 229
 230         for (Index = 0; Index < DATA_LENGTH; Index++)
 231                 Data[Index] = 0x50500A0A;
 232         xil_printf("    initialize Data done:\r\n");
 233
 234         Xil_DCacheFlush();
 235         xil_printf("    flush all done\r\n");
 236         dsb();
 237         #ifdef __aarch64__
 238                 CtrlReg = mfcp(SCTLR_EL3);
 239                 CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
 240                 mtcp(SCTLR_EL3,CtrlReg);
 241         #else
 242                 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 243                 CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
 244                 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 245         #endif
 246         dsb();
 247         Status = 0;
 248
 249         for (Index = 0; Index < DATA_LENGTH; Index++) {
 250                 Value = Data[Index];
 251
 252                 if (Value != 0x50500A0A) {
 253                         Status = -1;
 254                         xil_printf("Data[%d] = %x\r\n", Index, Value);
 255                         break;
 256                 }
 257         }
 258
 259         if (!Status) {
 260                 xil_printf("    Flush all worked\r\n");
 261         }
 262         else {
 263                 xil_printf("Error: Flush dcache all not working\r\n");
 264         }
 265         dsb();
 266         #ifdef __aarch64__
 267                 CtrlReg = mfcp(SCTLR_EL3);
 268                 CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
 269                 mtcp(SCTLR_EL3,CtrlReg);
 270         #else
 271                 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 272                         CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
 273                         mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 274         #endif
 275         dsb();
 276         for (Index = 0; Index < DATA_LENGTH; Index++)
 277                 Data[Index] = 0x505FFA0A;
 278
 279         Xil_DCacheFlush();
 280
 281
 282         for (Index = 0; Index < DATA_LENGTH; Index++)
 283                 Data[Index] = Index + 3;
 284
 285         Xil_DCacheInvalidate();
 286
 287         xil_printf("    invalidate all done\r\n");
 288         dsb();
 289         #ifdef __aarch64__
 290                 CtrlReg = mfcp(SCTLR_EL3);
 291                 CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
 292                 mtcp(SCTLR_EL3,CtrlReg);
 293         #else
 294                 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 295                 CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
 296                 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 297         #endif
 298         dsb();
 299         for (Index = 0; Index < DATA_LENGTH; Index++)
 300                 Data[Index] = 0x50CFA0A;
 301         dsb();
 302         #ifdef __aarch64__
 303                 CtrlReg = mfcp(SCTLR_EL3);
 304                 CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
 305                 mtcp(SCTLR_EL3,CtrlReg);
 306         #else
 307                 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
 308                 CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
 309                 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
 310         #endif
 311         dsb();
 312         Status = 0;
 313
 314         for (Index = 0; Index < DATA_LENGTH; Index++) {
 315                 Value = Data[Index];
 316                 if (Value != 0x50CFA0A) {
 317                         Status = -1;
 318                         xil_printf("Data[%d] = %x\r\n", Index, Value);
 319                         break;
 320                 }
 321         }
 322
 323         if (!Status) {
 324                 xil_printf("    Invalidate all worked\r\n");
 325         }
 326         else {
 327                         xil_printf("Error: Invalidate dcache all not working\r\n");
 328         }
 329
 330         xil_printf("-- DCache all Test Complete --\n\r");
 331
 332         return Status;
 333 }
 334
 335 /*****************************************************************************/
 336 /**
 337 * @brief   Perform Xil_ICacheInvalidateRange() on a few function pointers.
 338 *
 339 * @return
 340 *     - 0 is returned for a pass
 341 * @note
 342 *     The function will hang if it fails.
 343 *****************************************************************************/
 344 s32 Xil_TestICacheRange(void)
 345 {
 346
 347         Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
 348         Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
 349         Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
 350
 351         xil_printf("-- Invalidate icache range done --\r\n");
 352
 353         return 0;
 354 }
 355
 356 /*****************************************************************************/
 357 /**
 358 * @brief     Perform Xil_ICacheInvalidate() on a few function pointers.
 359 *
 360 * @return
 361 *           - 0 is returned for a pass
 362 * @note
 363 * The function will hang if it fails.
 364 *****************************************************************************/
 365 s32 Xil_TestICacheAll(void)
 366 {
 367         Xil_ICacheInvalidate();
 368         xil_printf("-- Invalidate icache all done --\r\n");
 369         return 0;
 370 }
 371 #endif