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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 * @file xparameters_ps.h
  35 *
  36 * This file contains the address definitions for the hard peripherals
  37 * attached to the ARM Cortex A9 core.
  38 *
  39 * <pre>
  40 * MODIFICATION HISTORY:
  41 *
  42 * Ver   Who     Date     Changes
  43 * ----- ------- -------- ---------------------------------------------------
  44 * 1.00a ecm/sdm 02/01/10 Initial version
  45 * 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
  46 *                        driver tcl
  47 * 5.0   pkp             01/16/15 Added interrupt ID definition of ttc for TEST APP
  48 * 6.6   srm     10/18/17 Added ARMA9 macro to identify CortexA9
  49 *
  50 * </pre>
  51 *
  52 * @note
  53 *
  54 * None.
  55 *
  56 ******************************************************************************/
  57
  58 #ifndef _XPARAMETERS_PS_H_
  59 #define _XPARAMETERS_PS_H_
  60
  61 #ifdef __cplusplus
  62 extern "C" {
  63 #endif
  64
  65 /****************************  Include Files  *******************************/
  66
  67
  68 /************************** Constant Definitions *****************************/
  69
  70 /*
  71  * This block contains constant declarations for the peripherals
  72  * within the hardblock
  73  */
  74
  75 /* Canonical definitions for DDR MEMORY */
  76 #define XPAR_DDR_MEM_BASEADDR           0x00000000U
  77 #define XPAR_DDR_MEM_HIGHADDR           0x3FFFFFFFU
  78
  79 /* Canonical definitions for Interrupts  */
  80 #define XPAR_XUARTPS_0_INTR             XPS_UART0_INT_ID
  81 #define XPAR_XUARTPS_1_INTR             XPS_UART1_INT_ID
  82 #define XPAR_XUSBPS_0_INTR              XPS_USB0_INT_ID
  83 #define XPAR_XUSBPS_1_INTR              XPS_USB1_INT_ID
  84 #define XPAR_XIICPS_0_INTR              XPS_I2C0_INT_ID
  85 #define XPAR_XIICPS_1_INTR              XPS_I2C1_INT_ID
  86 #define XPAR_XSPIPS_0_INTR              XPS_SPI0_INT_ID
  87 #define XPAR_XSPIPS_1_INTR              XPS_SPI1_INT_ID
  88 #define XPAR_XCANPS_0_INTR              XPS_CAN0_INT_ID
  89 #define XPAR_XCANPS_1_INTR              XPS_CAN1_INT_ID
  90 #define XPAR_XGPIOPS_0_INTR             XPS_GPIO_INT_ID
  91 #define XPAR_XEMACPS_0_INTR             XPS_GEM0_INT_ID
  92 #define XPAR_XEMACPS_0_WAKE_INTR        XPS_GEM0_WAKE_INT_ID
  93 #define XPAR_XEMACPS_1_INTR             XPS_GEM1_INT_ID
  94 #define XPAR_XEMACPS_1_WAKE_INTR        XPS_GEM1_WAKE_INT_ID
  95 #define XPAR_XSDIOPS_0_INTR             XPS_SDIO0_INT_ID
  96 #define XPAR_XQSPIPS_0_INTR             XPS_QSPI_INT_ID
  97 #define XPAR_XSDIOPS_1_INTR             XPS_SDIO1_INT_ID
  98 #define XPAR_XWDTPS_0_INTR              XPS_WDT_INT_ID
  99 #define XPAR_XDCFG_0_INTR               XPS_DVC_INT_ID
 100 #define XPAR_SCUTIMER_INTR              XPS_SCU_TMR_INT_ID
 101 #define XPAR_SCUWDT_INTR                XPS_SCU_WDT_INT_ID
 102 #define XPAR_XTTCPS_0_INTR              XPS_TTC0_0_INT_ID
 103 #define XPAR_XTTCPS_1_INTR              XPS_TTC0_1_INT_ID
 104 #define XPAR_XTTCPS_2_INTR              XPS_TTC0_2_INT_ID
 105 #define XPAR_XTTCPS_3_INTR              XPS_TTC1_0_INT_ID
 106 #define XPAR_XTTCPS_4_INTR              XPS_TTC1_1_INT_ID
 107 #define XPAR_XTTCPS_5_INTR              XPS_TTC1_2_INT_ID
 108 #define XPAR_XDMAPS_0_FAULT_INTR        XPS_DMA0_ABORT_INT_ID
 109 #define XPAR_XDMAPS_0_DONE_INTR_0       XPS_DMA0_INT_ID
 110 #define XPAR_XDMAPS_0_DONE_INTR_1       XPS_DMA1_INT_ID
 111 #define XPAR_XDMAPS_0_DONE_INTR_2       XPS_DMA2_INT_ID
 112 #define XPAR_XDMAPS_0_DONE_INTR_3       XPS_DMA3_INT_ID
 113 #define XPAR_XDMAPS_0_DONE_INTR_4       XPS_DMA4_INT_ID
 114 #define XPAR_XDMAPS_0_DONE_INTR_5       XPS_DMA5_INT_ID
 115 #define XPAR_XDMAPS_0_DONE_INTR_6       XPS_DMA6_INT_ID
 116 #define XPAR_XDMAPS_0_DONE_INTR_7       XPS_DMA7_INT_ID
 117
 118
 119 #define XPAR_XQSPIPS_0_LINEAR_BASEADDR  XPS_QSPI_LINEAR_BASEADDR
 120 #define XPAR_XPARPORTPS_CTRL_BASEADDR   XPS_PARPORT_CRTL_BASEADDR
 121
 122
 123
 124 /* Canonical definitions for DMAC */
 125
 126
 127 /* Canonical definitions for WDT */
 128
 129 /* Canonical definitions for SLCR */
 130 #define XPAR_XSLCR_NUM_INSTANCES        1U
 131 #define XPAR_XSLCR_0_DEVICE_ID          0U
 132 #define XPAR_XSLCR_0_BASEADDR           XPS_SYS_CTRL_BASEADDR
 133
 134 /* Canonical definitions for SCU GIC */
 135 #define XPAR_SCUGIC_NUM_INSTANCES       1U
 136 #define XPAR_SCUGIC_SINGLE_DEVICE_ID    0U
 137 #define XPAR_SCUGIC_CPU_BASEADDR        (XPS_SCU_PERIPH_BASE + 0x00000100U)
 138 #define XPAR_SCUGIC_DIST_BASEADDR       (XPS_SCU_PERIPH_BASE + 0x00001000U)
 139 #define XPAR_SCUGIC_ACK_BEFORE          0U
 140
 141 /* Canonical definitions for Global Timer */
 142 #define XPAR_GLOBAL_TMR_NUM_INSTANCES   1U
 143 #define XPAR_GLOBAL_TMR_DEVICE_ID       0U
 144 #define XPAR_GLOBAL_TMR_BASEADDR        (XPS_SCU_PERIPH_BASE + 0x00000200U)
 145 #define XPAR_GLOBAL_TMR_INTR            XPS_GLOBAL_TMR_INT_ID
 146
 147
 148 /* Xilinx Parallel Flash Library (XilFlash) User Settings */
 149 #define XPAR_AXI_EMC
 150
 151
 152 #define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
 153
 154
 155 /*
 156  * This block contains constant declarations for the peripherals
 157  * within the hardblock. These have been put for bacwards compatibilty
 158  */
 159
 160 #define XPS_PERIPHERAL_BASEADDR         0xE0000000U
 161 #define XPS_UART0_BASEADDR              0xE0000000U
 162 #define XPS_UART1_BASEADDR              0xE0001000U
 163 #define XPS_USB0_BASEADDR               0xE0002000U
 164 #define XPS_USB1_BASEADDR               0xE0003000U
 165 #define XPS_I2C0_BASEADDR               0xE0004000U
 166 #define XPS_I2C1_BASEADDR               0xE0005000U
 167 #define XPS_SPI0_BASEADDR               0xE0006000U
 168 #define XPS_SPI1_BASEADDR               0xE0007000U
 169 #define XPS_CAN0_BASEADDR               0xE0008000U
 170 #define XPS_CAN1_BASEADDR               0xE0009000U
 171 #define XPS_GPIO_BASEADDR               0xE000A000U
 172 #define XPS_GEM0_BASEADDR               0xE000B000U
 173 #define XPS_GEM1_BASEADDR               0xE000C000U
 174 #define XPS_QSPI_BASEADDR               0xE000D000U
 175 #define XPS_PARPORT_CRTL_BASEADDR       0xE000E000U
 176 #define XPS_SDIO0_BASEADDR              0xE0100000U
 177 #define XPS_SDIO1_BASEADDR              0xE0101000U
 178 #define XPS_IOU_BUS_CFG_BASEADDR        0xE0200000U
 179 #define XPS_NAND_BASEADDR               0xE1000000U
 180 #define XPS_PARPORT0_BASEADDR           0xE2000000U
 181 #define XPS_PARPORT1_BASEADDR           0xE4000000U
 182 #define XPS_QSPI_LINEAR_BASEADDR        0xFC000000U
 183 #define XPS_SYS_CTRL_BASEADDR           0xF8000000U     /* AKA SLCR */
 184 #define XPS_TTC0_BASEADDR               0xF8001000U
 185 #define XPS_TTC1_BASEADDR               0xF8002000U
 186 #define XPS_DMAC0_SEC_BASEADDR          0xF8003000U
 187 #define XPS_DMAC0_NON_SEC_BASEADDR      0xF8004000U
 188 #define XPS_WDT_BASEADDR                0xF8005000U
 189 #define XPS_DDR_CTRL_BASEADDR           0xF8006000U
 190 #define XPS_DEV_CFG_APB_BASEADDR        0xF8007000U
 191 #define XPS_AFI0_BASEADDR               0xF8008000U
 192 #define XPS_AFI1_BASEADDR               0xF8009000U
 193 #define XPS_AFI2_BASEADDR               0xF800A000U
 194 #define XPS_AFI3_BASEADDR               0xF800B000U
 195 #define XPS_OCM_BASEADDR                0xF800C000U
 196 #define XPS_EFUSE_BASEADDR              0xF800D000U
 197 #define XPS_CORESIGHT_BASEADDR          0xF8800000U
 198 #define XPS_TOP_BUS_CFG_BASEADDR        0xF8900000U
 199 #define XPS_SCU_PERIPH_BASE             0xF8F00000U
 200 #define XPS_L2CC_BASEADDR               0xF8F02000U
 201 #define XPS_SAM_RAM_BASEADDR            0xFFFC0000U
 202 #define XPS_FPGA_AXI_S0_BASEADDR        0x40000000U
 203 #define XPS_FPGA_AXI_S1_BASEADDR        0x80000000U
 204 #define XPS_IOU_S_SWITCH_BASEADDR       0xE0000000U
 205 #define XPS_PERIPH_APB_BASEADDR         0xF8000000U
 206
 207 /* Shared Peripheral Interrupts (SPI) */
 208 #define XPS_CORE_PARITY0_INT_ID         32U
 209 #define XPS_CORE_PARITY1_INT_ID         33U
 210 #define XPS_L2CC_INT_ID                 34U
 211 #define XPS_OCMINTR_INT_ID              35U
 212 #define XPS_ECC_INT_ID                  36U
 213 #define XPS_PMU0_INT_ID                 37U
 214 #define XPS_PMU1_INT_ID                 38U
 215 #define XPS_SYSMON_INT_ID               39U
 216 #define XPS_DVC_INT_ID                  40U
 217 #define XPS_WDT_INT_ID                  41U
 218 #define XPS_TTC0_0_INT_ID               42U
 219 #define XPS_TTC0_1_INT_ID               43U
 220 #define XPS_TTC0_2_INT_ID               44U
 221 #define XPS_DMA0_ABORT_INT_ID           45U
 222 #define XPS_DMA0_INT_ID                 46U
 223 #define XPS_DMA1_INT_ID                 47U
 224 #define XPS_DMA2_INT_ID                 48U
 225 #define XPS_DMA3_INT_ID                 49U
 226 #define XPS_SMC_INT_ID                  50U
 227 #define XPS_QSPI_INT_ID                 51U
 228 #define XPS_GPIO_INT_ID                 52U
 229 #define XPS_USB0_INT_ID                 53U
 230 #define XPS_GEM0_INT_ID                 54U
 231 #define XPS_GEM0_WAKE_INT_ID            55U
 232 #define XPS_SDIO0_INT_ID                56U
 233 #define XPS_I2C0_INT_ID                 57U
 234 #define XPS_SPI0_INT_ID                 58U
 235 #define XPS_UART0_INT_ID                59U
 236 #define XPS_CAN0_INT_ID                 60U
 237 #define XPS_FPGA0_INT_ID                61U
 238 #define XPS_FPGA1_INT_ID                62U
 239 #define XPS_FPGA2_INT_ID                63U
 240 #define XPS_FPGA3_INT_ID                64U
 241 #define XPS_FPGA4_INT_ID                65U
 242 #define XPS_FPGA5_INT_ID                66U
 243 #define XPS_FPGA6_INT_ID                67U
 244 #define XPS_FPGA7_INT_ID                68U
 245 #define XPS_TTC1_0_INT_ID               69U
 246 #define XPS_TTC1_1_INT_ID               70U
 247 #define XPS_TTC1_2_INT_ID               71U
 248 #define XPS_DMA4_INT_ID                 72U
 249 #define XPS_DMA5_INT_ID                 73U
 250 #define XPS_DMA6_INT_ID                 74U
 251 #define XPS_DMA7_INT_ID                 75U
 252 #define XPS_USB1_INT_ID                 76U
 253 #define XPS_GEM1_INT_ID                 77U
 254 #define XPS_GEM1_WAKE_INT_ID            78U
 255 #define XPS_SDIO1_INT_ID                79U
 256 #define XPS_I2C1_INT_ID                 80U
 257 #define XPS_SPI1_INT_ID                 81U
 258 #define XPS_UART1_INT_ID                82U
 259 #define XPS_CAN1_INT_ID                 83U
 260 #define XPS_FPGA8_INT_ID                84U
 261 #define XPS_FPGA9_INT_ID                85U
 262 #define XPS_FPGA10_INT_ID               86U
 263 #define XPS_FPGA11_INT_ID               87U
 264 #define XPS_FPGA12_INT_ID               88U
 265 #define XPS_FPGA13_INT_ID               89U
 266 #define XPS_FPGA14_INT_ID               90U
 267 #define XPS_FPGA15_INT_ID               91U
 268
 269 /* Private Peripheral Interrupts (PPI) */
 270 #define XPS_GLOBAL_TMR_INT_ID           27U     /* SCU Global Timer interrupt */
 271 #define XPS_FIQ_INT_ID                  28U     /* FIQ from FPGA fabric */
 272 #define XPS_SCU_TMR_INT_ID              29U     /* SCU Private Timer interrupt */
 273 #define XPS_SCU_WDT_INT_ID              30U     /* SCU Private WDT interrupt */
 274 #define XPS_IRQ_INT_ID                  31U     /* IRQ from FPGA fabric */
 275
 276
 277 /* REDEFINES for TEST APP */
 278 /* Definitions for UART */
 279 #define XPAR_PS7_UART_0_INTR            XPS_UART0_INT_ID
 280 #define XPAR_PS7_UART_1_INTR            XPS_UART1_INT_ID
 281 #define XPAR_PS7_USB_0_INTR             XPS_USB0_INT_ID
 282 #define XPAR_PS7_USB_1_INTR             XPS_USB1_INT_ID
 283 #define XPAR_PS7_I2C_0_INTR             XPS_I2C0_INT_ID
 284 #define XPAR_PS7_I2C_1_INTR             XPS_I2C1_INT_ID
 285 #define XPAR_PS7_SPI_0_INTR             XPS_SPI0_INT_ID
 286 #define XPAR_PS7_SPI_1_INTR             XPS_SPI1_INT_ID
 287 #define XPAR_PS7_CAN_0_INTR             XPS_CAN0_INT_ID
 288 #define XPAR_PS7_CAN_1_INTR             XPS_CAN1_INT_ID
 289 #define XPAR_PS7_GPIO_0_INTR            XPS_GPIO_INT_ID
 290 #define XPAR_PS7_ETHERNET_0_INTR        XPS_GEM0_INT_ID
 291 #define XPAR_PS7_ETHERNET_0_WAKE_INTR   XPS_GEM0_WAKE_INT_ID
 292 #define XPAR_PS7_ETHERNET_1_INTR        XPS_GEM1_INT_ID
 293 #define XPAR_PS7_ETHERNET_1_WAKE_INTR   XPS_GEM1_WAKE_INT_ID
 294 #define XPAR_PS7_QSPI_0_INTR            XPS_QSPI_INT_ID
 295 #define XPAR_PS7_WDT_0_INTR             XPS_WDT_INT_ID
 296 #define XPAR_PS7_SCUWDT_0_INTR          XPS_SCU_WDT_INT_ID
 297 #define XPAR_PS7_SCUTIMER_0_INTR        XPS_SCU_TMR_INT_ID
 298 #define XPAR_PS7_XADC_0_INTR            XPS_SYSMON_INT_ID
 299 #define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
 300 #define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
 301 #define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
 302 #define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
 303 #define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
 304 #define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
 305
 306 #define XPAR_XADCPS_INT_ID              XPS_SYSMON_INT_ID
 307
 308 /* For backwards compatibilty */
 309 #define XPAR_XUARTPS_0_CLOCK_HZ         XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
 310 #define XPAR_XUARTPS_1_CLOCK_HZ         XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
 311 #define XPAR_XTTCPS_0_CLOCK_HZ          XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
 312 #define XPAR_XTTCPS_1_CLOCK_HZ          XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
 313 #define XPAR_XTTCPS_2_CLOCK_HZ          XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
 314 #define XPAR_XTTCPS_3_CLOCK_HZ          XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
 315 #define XPAR_XTTCPS_4_CLOCK_HZ          XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
 316 #define XPAR_XTTCPS_5_CLOCK_HZ          XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
 317 #define XPAR_XIICPS_0_CLOCK_HZ          XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
 318 #define XPAR_XIICPS_1_CLOCK_HZ          XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
 319
 320 #define XPAR_XQSPIPS_0_CLOCK_HZ         XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
 321
 322 #ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
 323 #define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
 324 #endif
 325
 326 #ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
 327 #define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ    XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
 328 #endif
 329
 330 #define XPAR_SCUTIMER_DEVICE_ID         0U
 331 #define XPAR_SCUWDT_DEVICE_ID           0U
 332
 333
 334 #ifdef __cplusplus
 335 }
 336 #endif
 337
 338 #endif /* protection macro */