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37 * @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
39 * Cortex A9 event counter functions can be utilized to configure and control
40 * the Cortex-A9 performance monitor events.
42 * Cortex-A9 performance monitor has six event counters which can be used to
43 * count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
44 * configurations XPM_CNTRCFGx which can be used to program the event counters
45 * to count a set of events.
48 * It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
49 * being used for time keeping.
54 * MODIFICATION HISTORY:
56 * Ver Who Date Changes
57 * ----- ---- -------- -----------------------------------------------
58 * 1.00a sdm 07/11/11 First release
61 ******************************************************************************/
63 #ifndef XPMCOUNTER_H /* prevent circular inclusions */
64 #define XPMCOUNTER_H /* by using protection macros */
66 /***************************** Include Files ********************************/
69 #include "xpseudo_asm.h"
70 #include "xil_types.h"
74 #endif /* __cplusplus */
76 /************************** Constant Definitions ****************************/
78 /* Number of performance counters */
79 #define XPM_CTRCOUNT 6U
81 /* The following constants define the Cortex-A9 Performance Monitor Events */
84 * Software increment. The register is incremented only on writes to the
85 * Software Increment Register
87 #define XPM_EVENT_SOFTINCR 0x00U
90 * Instruction fetch that causes a refill at (at least) the lowest level(s) of
91 * instruction or unified cache. Includes the speculative linefills in the
94 #define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
97 * Instruction fetch that causes a TLB refill at (at least) the lowest level of
98 * TLB. Includes the speculative requests in the count
100 #define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
103 * Data read or write operation that causes a refill at (at least) the lowest
104 * level(s)of data or unified cache. Counts the number of allocations performed
105 * in the Data Cache due to a read or a write
107 #define XPM_EVENT_DATA_CACHEREFILL 0x03U
110 * Data read or write operation that causes a cache access at (at least) the
111 * lowest level(s) of data or unified cache. This includes speculative reads
113 #define XPM_EVENT_DATA_CACHEACCESS 0x04U
116 * Data read or write operation that causes a TLB refill at (at least) the
117 * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
118 * CP15 Cache operation by MVA and CP15 VA to PA operations
120 #define XPM_EVENT_DATA_TLBREFILL 0x05U
123 * Data read architecturally executed. Counts the number of data read
124 * instructions accepted by the Load Store Unit. This includes counting the
125 * speculative and aborted LDR/LDM, as well as the reads due to the SWP
128 #define XPM_EVENT_DATA_READS 0x06U
131 * Data write architecturally executed. Counts the number of data write
132 * instructions accepted by the Load Store Unit. This includes counting the
133 * speculative and aborted STR/STM, as well as the writes due to the SWP
136 #define XPM_EVENT_DATA_WRITE 0x07U
138 /* Exception taken. Counts the number of exceptions architecturally taken.*/
139 #define XPM_EVENT_EXCEPTION 0x09U
141 /* Exception return architecturally executed.*/
142 #define XPM_EVENT_EXCEPRETURN 0x0AU
145 * Change to ContextID retired. Counts the number of instructions
146 * architecturally executed writing into the ContextID Register
148 #define XPM_EVENT_CHANGECONTEXT 0x0BU
151 * Software change of PC, except by an exception, architecturally executed.
152 * Count the number of PC changes architecturally executed, excluding the PC
153 * changes due to taken exceptions
155 #define XPM_EVENT_SW_CHANGEPC 0x0CU
158 * Immediate branch architecturally executed (taken or not taken). This includes
159 * the branches which are flushed due to a previous load/store which aborts
162 #define XPM_EVENT_IMMEDBRANCH 0x0DU
165 * Unaligned access architecturally executed. Counts the number of aborted
166 * unaligned accessed architecturally executed, and the number of not-aborted
167 * unaligned accesses, including the speculative ones
169 #define XPM_EVENT_UNALIGNEDACCESS 0x0FU
172 * Branch mispredicted/not predicted. Counts the number of mispredicted or
173 * not-predicted branches executed. This includes the branches which are flushed
174 * due to a previous load/store which aborts late
176 #define XPM_EVENT_BRANCHMISS 0x10U
179 * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
180 * event is not exported on the PMUEVENT bus
182 #define XPM_EVENT_CLOCKCYCLES 0x11U
185 * Branches or other change in program flow that could have been predicted by
186 * the branch prediction resources of the processor. This includes the branches
187 * which are flushed due to a previous load/store which aborts late
189 #define XPM_EVENT_BRANCHPREDICT 0x12U
192 * Java bytecode execute. Counts the number of Java bytecodes being decoded,
193 * including speculative ones
195 #define XPM_EVENT_JAVABYTECODE 0x40U
198 * Software Java bytecode executed. Counts the number of software java bytecodes
199 * being decoded, including speculative ones
201 #define XPM_EVENT_SWJAVABYTECODE 0x41U
204 * Jazelle backward branches executed. Counts the number of Jazelle taken
205 * branches being executed. This includes the branches which are flushed due
206 * to a previous load/store which aborts late
208 #define XPM_EVENT_JAVABACKBRANCH 0x42U
211 * Coherent linefill miss Counts the number of coherent linefill requests
212 * performed by the Cortex-A9 processor which also miss in all the other
213 * Cortex-A9 processors, meaning that the request is sent to the external
216 #define XPM_EVENT_COHERLINEMISS 0x50U
219 * Coherent linefill hit. Counts the number of coherent linefill requests
220 * performed by the Cortex-A9 processor which hit in another Cortex-A9
221 * processor, meaning that the linefill data is fetched directly from the
222 * relevant Cortex-A9 cache
224 #define XPM_EVENT_COHERLINEHIT 0x51U
227 * Instruction cache dependent stall cycles. Counts the number of cycles where
228 * the processor is ready to accept new instructions, but does not receive any
229 * due to the instruction side not being able to provide any and the
230 * instruction cache is currently performing at least one linefill
232 #define XPM_EVENT_INSTRSTALL 0x60U
235 * Data cache dependent stall cycles. Counts the number of cycles where the core
236 * has some instructions that it cannot issue to any pipeline, and the Load
237 * Store unit has at least one pending linefill request, and no pending
239 #define XPM_EVENT_DATASTALL 0x61U
242 * Main TLB miss stall cycles. Counts the number of cycles where the processor
243 * is stalled waiting for the completion of translation table walks from the
244 * main TLB. The processor stalls can be due to the instruction side not being
245 * able to provide the instructions, or to the data side not being able to
246 * provide the necessary data, due to them waiting for the main TLB translation
247 * table walk to complete
249 #define XPM_EVENT_MAINTLBSTALL 0x62U
252 * Counts the number of STREX instructions architecturally executed and
255 #define XPM_EVENT_STREXPASS 0x63U
258 * Counts the number of STREX instructions architecturally executed and
261 #define XPM_EVENT_STREXFAIL 0x64U
264 * Data eviction. Counts the number of eviction requests due to a linefill in
267 #define XPM_EVENT_DATAEVICT 0x65U
270 * Counts the number of cycles where the issue stage does not dispatch any
271 * instruction because it is empty or cannot dispatch any instructions
273 #define XPM_EVENT_NODISPATCH 0x66U
276 * Counts the number of cycles where the issue stage is empty
278 #define XPM_EVENT_ISSUEEMPTY 0x67U
281 * Counts the number of instructions going through the Register Renaming stage.
282 * This number is an approximate number of the total number of instructions
283 * speculatively executed, and even more approximate of the total number of
284 * instructions architecturally executed. The approximation depends mainly on
285 * the branch misprediction rate.
286 * The renaming stage can handle two instructions in the same cycle so the event
288 * - b00 no instructions renamed
289 * - b01 one instruction renamed
290 * - b10 two instructions renamed
292 #define XPM_EVENT_INSTRRENAME 0x68U
295 * Counts the number of procedure returns whose condition codes do not fail,
296 * excluding all returns from exception. This count includes procedure returns
297 * which are flushed due to a previous load/store which aborts late.
298 * Only the following instructions are reported:
302 * - LDR pc,[sp],#offset
303 * The following instructions are not reported:
304 * - LDMIA R9!,{..,PC} (ThumbEE state only)
305 * - LDR PC,[R9],#offset (ThumbEE state only)
306 * - BX R0 (Rm != R14)
307 * - MOV PC,R0 (Rm != R14)
308 * - LDM SP,{...,PC} (writeback not specified)
309 * - LDR PC,[SP,#offset] (wrong addressing mode)
311 #define XPM_EVENT_PREDICTFUNCRET 0x6EU
314 * Counts the number of instructions being executed in the main execution
315 * pipeline of the processor, the multiply pipeline and arithmetic logic unit
316 * pipeline. The counted instructions are still speculative
318 #define XPM_EVENT_MAINEXEC 0x70U
321 * Counts the number of instructions being executed in the processor second
322 * execution pipeline (ALU). The counted instructions are still speculative
324 #define XPM_EVENT_SECEXEC 0x71U
327 * Counts the number of instructions being executed in the Load/Store unit. The
328 * counted instructions are still speculative
330 #define XPM_EVENT_LDRSTR 0x72U
333 * Counts the number of Floating-point instructions going through the Register
334 * Rename stage. Instructions are still speculative in this stage.
335 *Two floating-point instructions can be renamed in the same cycle so the event
337 *0b00 no floating-point instruction renamed
338 *0b01 one floating-point instruction renamed
339 *0b10 two floating-point instructions renamed
341 #define XPM_EVENT_FLOATRENAME 0x73U
344 * Counts the number of Neon instructions going through the Register Rename
345 * stage.Instructions are still speculative in this stage.
346 * Two NEON instructions can be renamed in the same cycle so the event is two
348 *0b00 no NEON instruction renamed
349 *0b01 one NEON instruction renamed
350 *0b10 two NEON instructions renamed
352 #define XPM_EVENT_NEONRENAME 0x74U
355 * Counts the number of cycles where the processor is stalled because PLD slots
358 #define XPM_EVENT_PLDSTALL 0x80U
361 * Counts the number of cycles when the processor is stalled and the data side
362 * is stalled too because it is full and executing writes to the external
365 #define XPM_EVENT_WRITESTALL 0x81U
368 * Counts the number of stall cycles due to main TLB misses on requests issued
369 * by the instruction side
371 #define XPM_EVENT_INSTRTLBSTALL 0x82U
374 * Counts the number of stall cycles due to main TLB misses on requests issued
377 #define XPM_EVENT_DATATLBSTALL 0x83U
380 * Counts the number of stall cycles due to micro TLB misses on the instruction
381 * side. This event does not include main TLB miss stall cycles that are already
382 * counted in the corresponding main TLB event
384 #define XPM_EVENT_INSTR_uTLBSTALL 0x84U
387 * Counts the number of stall cycles due to micro TLB misses on the data side.
388 * This event does not include main TLB miss stall cycles that are already
389 * counted in the corresponding main TLB event
391 #define XPM_EVENT_DATA_uTLBSTALL 0x85U
394 * Counts the number of stall cycles because of the execution of a DMB memory
395 * barrier. This includes all DMB instructions being executed, even
398 #define XPM_EVENT_DMB_STALL 0x86U
401 * Counts the number of cycles during which the integer core clock is enabled
403 #define XPM_EVENT_INT_CLKEN 0x8AU
406 * Counts the number of cycles during which the Data Engine clock is enabled
408 #define XPM_EVENT_DE_CLKEN 0x8BU
411 * Counts the number of ISB instructions architecturally executed
413 #define XPM_EVENT_INSTRISB 0x90U
416 * Counts the number of DSB instructions architecturally executed
418 #define XPM_EVENT_INSTRDSB 0x91U
421 * Counts the number of DMB instructions speculatively executed
423 #define XPM_EVENT_INSTRDMB 0x92U
426 * Counts the number of external interrupts executed by the processor
428 #define XPM_EVENT_EXTINT 0x93U
431 * PLE cache line request completed
433 #define XPM_EVENT_PLE_LRC 0xA0U
436 * PLE cache line request skipped
438 #define XPM_EVENT_PLE_LRS 0xA1U
443 #define XPM_EVENT_PLE_FLUSH 0xA2U
446 * PLE request complete
448 #define XPM_EVENT_PLE_CMPL 0xA3U
453 #define XPM_EVENT_PLE_OVFL 0xA4U
456 * PLE request programmed
458 #define XPM_EVENT_PLE_PROG 0xA5U
461 * The following constants define the configurations for Cortex-A9 Performance
462 * Monitor Events. Each configuration configures the event counters for a set
464 * -----------------------------------------------
465 * Config PmCtr0... PmCtr5
466 * -----------------------------------------------
467 * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
468 * XPM_EVENT_INSRFETCH_CACHEREFILL,
469 * XPM_EVENT_INSTRFECT_TLBREFILL,
470 * XPM_EVENT_DATA_CACHEREFILL,
471 * XPM_EVENT_DATA_CACHEACCESS,
472 * XPM_EVENT_DATA_TLBREFILL }
474 * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
475 * XPM_EVENT_DATA_WRITE,
476 * XPM_EVENT_EXCEPTION,
477 * XPM_EVENT_EXCEPRETURN,
478 * XPM_EVENT_CHANGECONTEXT,
479 * XPM_EVENT_SW_CHANGEPC }
481 * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
482 * XPM_EVENT_UNALIGNEDACCESS,
483 * XPM_EVENT_BRANCHMISS,
484 * XPM_EVENT_CLOCKCYCLES,
485 * XPM_EVENT_BRANCHPREDICT,
486 * XPM_EVENT_JAVABYTECODE }
488 * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
489 * XPM_EVENT_JAVABACKBRANCH,
490 * XPM_EVENT_COHERLINEMISS,
491 * XPM_EVENT_COHERLINEHIT,
492 * XPM_EVENT_INSTRSTALL,
493 * XPM_EVENT_DATASTALL }
495 * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
496 * XPM_EVENT_STREXPASS,
497 * XPM_EVENT_STREXFAIL,
498 * XPM_EVENT_DATAEVICT,
499 * XPM_EVENT_NODISPATCH,
500 * XPM_EVENT_ISSUEEMPTY }
502 * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
503 * XPM_EVENT_PREDICTFUNCRET,
504 * XPM_EVENT_MAINEXEC,
507 * XPM_EVENT_FLOATRENAME }
509 * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
510 * XPM_EVENT_PLDSTALL,
511 * XPM_EVENT_WRITESTALL,
512 * XPM_EVENT_INSTRTLBSTALL,
513 * XPM_EVENT_DATATLBSTALL,
514 * XPM_EVENT_INSTR_uTLBSTALL }
516 * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
517 * XPM_EVENT_DMB_STALL,
518 * XPM_EVENT_INT_CLKEN,
519 * XPM_EVENT_DE_CLKEN,
520 * XPM_EVENT_INSTRISB,
521 * XPM_EVENT_INSTRDSB }
523 * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
527 * XPM_EVENT_PLE_FLUSH,
528 * XPM_EVENT_PLE_CMPL }
530 * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
531 * XPM_EVENT_PLE_PROG,
534 * XPM_EVENT_PLE_FLUSH,
535 * XPM_EVENT_PLE_CMPL }
537 * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
538 * XPM_EVENT_INSRFETCH_CACHEREFILL,
539 * XPM_EVENT_INSTRFECT_TLBREFILL,
540 * XPM_EVENT_DATA_CACHEREFILL,
541 * XPM_EVENT_DATA_CACHEACCESS,
542 * XPM_EVENT_DATA_TLBREFILL }
544 #define XPM_CNTRCFG1 0
545 #define XPM_CNTRCFG2 1
546 #define XPM_CNTRCFG3 2
547 #define XPM_CNTRCFG4 3
548 #define XPM_CNTRCFG5 4
549 #define XPM_CNTRCFG6 5
550 #define XPM_CNTRCFG7 6
551 #define XPM_CNTRCFG8 7
552 #define XPM_CNTRCFG9 8
553 #define XPM_CNTRCFG10 9
554 #define XPM_CNTRCFG11 10
556 /**************************** Type Definitions ******************************/
558 /***************** Macros (Inline Functions) Definitions ********************/
560 /************************** Variable Definitions ****************************/
562 /************************** Function Prototypes *****************************/
564 /* Interface fuctions to access perfromance counters from abstraction layer */
565 void Xpm_SetEvents(s32 PmcrCfg);
566 void Xpm_GetEventCounters(u32 *PmCtrValue);
574 * @} End of "addtogroup a9_event_counter_apis".