1 /******************************************************************************
3 * Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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31 ******************************************************************************/
32 /*****************************************************************************/
37 * This header file contains the hardware interface of an XUartPs device.
40 * MODIFICATION HISTORY:
42 * Ver Who Date Changes
43 * ----- ------ -------- ----------------------------------------------
44 * 1.00 drg/jz 01/12/10 First Release
45 * 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
46 * and XUARTPS_IXR_TTRIG.
47 * Modified the names of these defines
48 * XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
49 * XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
50 * XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
51 * XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
52 * 1.05a hk 08/22/13 Added prototype for uart reset and related
53 * constant definitions.
57 ******************************************************************************/
58 #ifndef XUARTPS_HW_H /* prevent circular inclusions */
59 #define XUARTPS_HW_H /* by using protection macros */
65 /***************************** Include Files *********************************/
67 #include "xil_types.h"
68 #include "xil_assert.h"
71 /************************** Constant Definitions *****************************/
73 /** @name Register Map
75 * Register offsets for the UART.
78 #define XUARTPS_CR_OFFSET 0x00 /**< Control Register [8:0] */
79 #define XUARTPS_MR_OFFSET 0x04 /**< Mode Register [9:0] */
80 #define XUARTPS_IER_OFFSET 0x08 /**< Interrupt Enable [12:0] */
81 #define XUARTPS_IDR_OFFSET 0x0C /**< Interrupt Disable [12:0] */
82 #define XUARTPS_IMR_OFFSET 0x10 /**< Interrupt Mask [12:0] */
83 #define XUARTPS_ISR_OFFSET 0x14 /**< Interrupt Status [12:0]*/
84 #define XUARTPS_BAUDGEN_OFFSET 0x18 /**< Baud Rate Generator [15:0] */
85 #define XUARTPS_RXTOUT_OFFSET 0x1C /**< RX Timeout [7:0] */
86 #define XUARTPS_RXWM_OFFSET 0x20 /**< RX FIFO Trigger Level [5:0] */
87 #define XUARTPS_MODEMCR_OFFSET 0x24 /**< Modem Control [5:0] */
88 #define XUARTPS_MODEMSR_OFFSET 0x28 /**< Modem Status [8:0] */
89 #define XUARTPS_SR_OFFSET 0x2C /**< Channel Status [14:0] */
90 #define XUARTPS_FIFO_OFFSET 0x30 /**< FIFO [7:0] */
91 #define XUARTPS_BAUDDIV_OFFSET 0x34 /**< Baud Rate Divider [7:0] */
92 #define XUARTPS_FLOWDEL_OFFSET 0x38 /**< Flow Delay [5:0] */
93 #define XUARTPS_TXWM_OFFSET 0x44 /**< TX FIFO Trigger Level [5:0] */
96 /** @name Control Register
98 * The Control register (CR) controls the major functions of the device.
100 * Control Register Bit Definition
103 #define XUARTPS_CR_STOPBRK 0x00000100 /**< Stop transmission of break */
104 #define XUARTPS_CR_STARTBRK 0x00000080 /**< Set break */
105 #define XUARTPS_CR_TORST 0x00000040 /**< RX timeout counter restart */
106 #define XUARTPS_CR_TX_DIS 0x00000020 /**< TX disabled. */
107 #define XUARTPS_CR_TX_EN 0x00000010 /**< TX enabled */
108 #define XUARTPS_CR_RX_DIS 0x00000008 /**< RX disabled. */
109 #define XUARTPS_CR_RX_EN 0x00000004 /**< RX enabled */
110 #define XUARTPS_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */
111 #define XUARTPS_CR_TXRST 0x00000002 /**< TX logic reset */
112 #define XUARTPS_CR_RXRST 0x00000001 /**< RX logic reset */
116 /** @name Mode Register
118 * The mode register (MR) defines the mode of transfer as well as the data
119 * format. If this register is modified during transmission or reception,
120 * data validity cannot be guaranteed.
122 * Mode Register Bit Definition
125 #define XUARTPS_MR_CCLK 0x00000400 /**< Input clock selection */
126 #define XUARTPS_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */
127 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */
128 #define XUARTPS_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */
129 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /**< Normal mode */
130 #define XUARTPS_MR_CHMODE_SHIFT 8 /**< Mode shift */
131 #define XUARTPS_MR_CHMODE_MASK 0x00000300 /**< Mode mask */
132 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */
133 #define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */
134 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */
135 #define XUARTPS_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */
136 #define XUARTPS_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */
137 #define XUARTPS_MR_PARITY_NONE 0x00000020 /**< No parity mode */
138 #define XUARTPS_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */
139 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */
140 #define XUARTPS_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */
141 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */
142 #define XUARTPS_MR_PARITY_SHIFT 3 /**< Parity setting shift */
143 #define XUARTPS_MR_PARITY_MASK 0x00000038 /**< Parity mask */
144 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */
145 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */
146 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */
147 #define XUARTPS_MR_CHARLEN_SHIFT 1 /**< Data Length shift */
148 #define XUARTPS_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */
149 #define XUARTPS_MR_CLKSEL 0x00000001 /**< Input clock selection */
153 /** @name Interrupt Registers
155 * Interrupt control logic uses the interrupt enable register (IER) and the
156 * interrupt disable register (IDR) to set the value of the bits in the
157 * interrupt mask register (IMR). The IMR determines whether to pass an
158 * interrupt to the interrupt status register (ISR).
159 * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
160 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
161 * Reading either IER or IDR returns 0x00.
163 * All four registers have the same bit definitions.
167 #define XUARTPS_IXR_TOVR 0x00001000 /**< Tx FIFO Overflow interrupt */
168 #define XUARTPS_IXR_TNFUL 0x00000800 /**< Tx FIFO Nearly Full interrupt */
169 #define XUARTPS_IXR_TTRIG 0x00000400 /**< Tx Trig interrupt */
170 #define XUARTPS_IXR_DMS 0x00000200 /**< Modem status change interrupt */
171 #define XUARTPS_IXR_TOUT 0x00000100 /**< Timeout error interrupt */
172 #define XUARTPS_IXR_PARITY 0x00000080 /**< Parity error interrupt */
173 #define XUARTPS_IXR_FRAMING 0x00000040 /**< Framing error interrupt */
174 #define XUARTPS_IXR_OVER 0x00000020 /**< Overrun error interrupt */
175 #define XUARTPS_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */
176 #define XUARTPS_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */
177 #define XUARTPS_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */
178 #define XUARTPS_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */
179 #define XUARTPS_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */
180 #define XUARTPS_IXR_MASK 0x00001FFF /**< Valid bit mask */
184 /** @name Baud Rate Generator Register
186 * The baud rate generator control register (BRGR) is a 16 bit register that
187 * controls the receiver bit sample clock and baud rate.
188 * Valid values are 1 - 65535.
190 * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
191 * in the MR register.
194 #define XUARTPS_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */
195 #define XUARTPS_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */
196 #define XUARTPS_BAUDGEN_RESET_VAL 0x0000028B /**< Reset value */
198 /** @name Baud Divisor Rate register
200 * The baud rate divider register (BDIV) controls how much the bit sample
201 * rate is divided by. It sets the baud rate.
202 * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
204 * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
205 * the MR_CCLK bit in the MR register.
208 #define XUARTPS_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */
209 #define XUARTPS_BAUDDIV_RESET_VAL 0x0000000F /**< Reset value */
213 /** @name Receiver Timeout Register
215 * Use the receiver timeout register (RTR) to detect an idle condition on
216 * the receiver data line.
220 #define XUARTPS_RXTOUT_DISABLE 0x00000000 /**< Disable time out */
221 #define XUARTPS_RXTOUT_MASK 0x000000FF /**< Valid bits mask */
223 /** @name Receiver FIFO Trigger Level Register
225 * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
226 * which the RX FIFO triggers an interrupt event.
230 #define XUARTPS_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */
231 #define XUARTPS_RXWM_MASK 0x0000003F /**< Valid bits mask */
232 #define XUARTPS_RXWM_RESET_VAL 0x00000020 /**< Reset value */
235 /** @name Transmit FIFO Trigger Level Register
237 * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
238 * which the TX FIFO triggers an interrupt event.
242 #define XUARTPS_TXWM_MASK 0x0000003F /**< Valid bits mask */
243 #define XUARTPS_TXWM_RESET_VAL 0x00000020 /**< Reset value */
246 /** @name Modem Control Register
248 * This register (MODEMCR) controls the interface with the modem or data set,
249 * or a peripheral device emulating a modem.
253 #define XUARTPS_MODEMCR_FCM 0x00000010 /**< Flow control mode */
254 #define XUARTPS_MODEMCR_RTS 0x00000002 /**< Request to send */
255 #define XUARTPS_MODEMCR_DTR 0x00000001 /**< Data terminal ready */
258 /** @name Modem Status Register
260 * This register (MODEMSR) indicates the current state of the control lines
261 * from a modem, or another peripheral device, to the CPU. In addition, four
262 * bits of the modem status register provide change information. These bits
263 * are set to a logic 1 whenever a control input from the modem changes state.
265 * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
266 * status interrupt is generated and this is reflected in the modem status
271 #define XUARTPS_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */
272 #define XUARTPS_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */
273 #define XUARTPS_MODEMSR_RI 0x00000040 /**< Complement of RI input */
274 #define XUARTPS_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */
275 #define XUARTPS_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */
276 #define XUARTPS_MODEMSR_DDCD 0x00000008 /**< Delta DCD indicator */
277 #define XUARTPS_MODEMSR_TERI 0x00000004 /**< Trailing Edge Ring Indicator */
278 #define XUARTPS_MODEMSR_DDSR 0x00000002 /**< Change of DSR */
279 #define XUARTPS_MODEMSR_DCTS 0x00000001 /**< Change of CTS */
282 /** @name Channel Status Register
284 * The channel status register (CSR) is provided to enable the control logic
285 * to monitor the status of bits in the channel interrupt status register,
286 * even if these are masked out by the interrupt mask register.
290 #define XUARTPS_SR_TNFUL 0x00004000 /**< TX FIFO Nearly Full Status */
291 #define XUARTPS_SR_TTRIG 0x00002000 /**< TX FIFO Trigger Status */
292 #define XUARTPS_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */
293 #define XUARTPS_SR_TACTIVE 0x00000800 /**< TX active */
294 #define XUARTPS_SR_RACTIVE 0x00000400 /**< RX active */
295 #define XUARTPS_SR_DMS 0x00000200 /**< Delta modem status change */
296 #define XUARTPS_SR_TOUT 0x00000100 /**< RX timeout */
297 #define XUARTPS_SR_PARITY 0x00000080 /**< RX parity error */
298 #define XUARTPS_SR_FRAME 0x00000040 /**< RX frame error */
299 #define XUARTPS_SR_OVER 0x00000020 /**< RX overflow error */
300 #define XUARTPS_SR_TXFULL 0x00000010 /**< TX FIFO full */
301 #define XUARTPS_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */
302 #define XUARTPS_SR_RXFULL 0x00000004 /**< RX FIFO full */
303 #define XUARTPS_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */
304 #define XUARTPS_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */
307 /** @name Flow Delay Register
309 * Operation of the flow delay register (FLOWDEL) is very similar to the
310 * receive FIFO trigger register. An internal trigger signal activates when the
311 * FIFO is filled to the level set by this register. This trigger will not
312 * cause an interrupt, although it can be read through the channel status
313 * register. In hardware flow control mode, RTS is deactivated when the trigger
314 * becomes active. RTS only resets when the FIFO level is four less than the
315 * level of the flow delay trigger and the flow delay trigger is not activated.
316 * A value less than 4 disables the flow delay.
319 #define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
325 * Defines for backwards compatabilty, will be removed
326 * in the next version of the driver
328 #define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
329 #define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
330 #define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
331 #define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
335 /**************************** Type Definitions *******************************/
338 /***************** Macros (Inline Functions) Definitions *********************/
340 /****************************************************************************/
342 * Read a UART register.
344 * @param BaseAddress contains the base address of the device.
345 * @param RegOffset contains the offset from the base address of the
348 * @return The value read from the register.
350 * @note C-Style signature:
351 * u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
353 ******************************************************************************/
354 #define XUartPs_ReadReg(BaseAddress, RegOffset) \
355 Xil_In32((BaseAddress) + (RegOffset))
357 /***************************************************************************/
359 * Write a UART register.
361 * @param BaseAddress contains the base address of the device.
362 * @param RegOffset contains the offset from the base address of the
364 * @param RegisterValue is the value to be written to the register.
368 * @note C-Style signature:
369 * void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
372 ******************************************************************************/
373 #define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
374 Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
376 /****************************************************************************/
378 * Determine if there is receive data in the receiver and/or FIFO.
380 * @param BaseAddress contains the base address of the device.
382 * @return TRUE if there is receive data, FALSE otherwise.
384 * @note C-Style signature:
385 * u32 XUartPs_IsReceiveData(u32 BaseAddress)
387 ******************************************************************************/
388 #define XUartPs_IsReceiveData(BaseAddress) \
389 !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
390 XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY)
392 /****************************************************************************/
394 * Determine if a byte of data can be sent with the transmitter.
396 * @param BaseAddress contains the base address of the device.
398 * @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
401 * @note C-Style signature:
402 * u32 XUartPs_IsTransmitFull(u32 BaseAddress)
404 ******************************************************************************/
405 #define XUartPs_IsTransmitFull(BaseAddress) \
406 ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
407 XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL)
409 /************************** Function Prototypes ******************************/
411 void XUartPs_SendByte(u32 BaseAddress, u8 Data);
413 u8 XUartPs_RecvByte(u32 BaseAddress);
415 void XUartPs_ResetHw(u32 BaseAddress);
417 /************************** Variable Definitions *****************************/
423 #endif /* end of protection macro */