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32 /*****************************************************************************/
36 * @addtogroup usbps_v2_1
39 * This header file contains identifiers and low-level driver functions (or
40 * macros) that can be used to access the device. High-level driver functions
41 * are defined in xusbps.h.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- -----------------------------------------------
48 * 1.00a wgr 10/10/10 First release
49 * 1.04a nm 10/23/12 Fixed CR# 679106.
50 * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
51 * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
54 ******************************************************************************/
62 /***************************** Include Files *********************************/
64 #include "xil_types.h"
65 #include "xil_assert.h"
68 /************************** Constant Definitions *****************************/
71 #define XUSBPS_REG_SPACING 4
73 /** @name Timer 0 Register offsets
77 #define XUSBPS_TIMER0_LD_OFFSET 0x00000080
78 #define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
81 /** @name Timer Control Register bit mask
85 #define XUSBPS_TIMER_RUN_MASK 0x80000000
86 #define XUSBPS_TIMER_STOP_MASK 0x80000000
87 #define XUSBPS_TIMER_RESET_MASK 0x40000000
88 #define XUSBPS_TIMER_REPEAT_MASK 0x01000000
91 /** @name Timer Control Register bit mask
95 #define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
98 /** @name Device Hardware Parameters
102 #define XUSBPS_HWDEVICE_OFFSET 0x0000000C
104 #define XUSBPS_EP_NUM_MASK 0x3E
105 #define XUSBPS_EP_NUM_SHIFT 1
108 /** @name Capability Regsiter offsets
110 #define XUSBPS_HCSPARAMS_OFFSET 0x00000104
112 /** @name Operational Register offsets.
113 * Register comments are tagged with "H:" and "D:" for Host and Device modes,
115 * Tags are only present for registers that have a different meaning DEVICE and
116 * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
117 * Those registers don't have tags.
120 #define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
121 #define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
122 #define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
123 #define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
124 #define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
125 #define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
126 #define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
127 #define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
128 #define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
129 #define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
130 #define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
131 #define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
132 #define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
133 #define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
134 #define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
136 /* NOTE: The Port Control / Status Register index is 1-based. */
137 #define XUSBPS_PORTSCRn_OFFSET(n) \
138 (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
141 #define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
142 #define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
143 #define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
144 #define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
145 #define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
146 #define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
147 #define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
148 #define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
149 #define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
150 #define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
151 #define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
152 #define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
154 #define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
156 #define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
157 #define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
158 #define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
160 #define XUSBPS_EPCRn_OFFSET(n) \
161 (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
163 #define XUSBPS_EPFLUSH_RX_SHIFT 0
164 #define XUSBPS_EPFLUSH_TX_SHIFT 16
170 /** @name Endpoint Control Register (EPCR) bit positions.
174 /* Definitions for TX Endpoint bits */
175 #define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
176 #define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
177 #define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
178 #define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
179 #define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
180 #define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
181 #define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
184 /* Definitions for RX Endpoint bits */
185 #define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
186 #define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
187 #define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
188 #define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
189 #define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
190 #define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
191 #define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
195 /** @name USB Command Register (CR) bit positions.
198 #define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
199 #define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
200 #define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
201 #define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
202 #define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
203 #define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
204 #define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
205 #define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
206 #define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
207 #define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
208 #define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
209 #define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
214 * @name Interrupt Threshold
215 * These definitions are used by software to set the maximum rate at which the
216 * USB controller will generate interrupt requests. The interrupt interval is
217 * given in number of micro-frames.
219 * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
220 * packet each and every 1ms. USB also defines a high-speed micro-frame with a
221 * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
222 * generated. Data is sent in between the SOF packets. The interrupt threshold
223 * defines how many micro-frames the controller waits before issuing an
224 * interrupt after data has been received.
226 * For a threshold of 0 the controller will issue an interrupt immediately
227 * after the last byte of the data has been received. For a threshold n>0 the
228 * controller will wait for n micro-frames before issuing an interrupt.
230 * Therefore, a setting of 8 micro-frames (default) means that the controller
231 * will issue at most 1 interrupt per millisecond.
235 #define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
236 #define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
237 #define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
238 #define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
239 #define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
240 #define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
241 #define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
242 #define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
243 #define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
244 #define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
249 /** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
253 #define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
254 #define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
255 #define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
256 #define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
257 #define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
258 #define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
259 #define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
260 #define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
261 #define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
262 #define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
264 #define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
265 #define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
267 #define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
268 #define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
269 #define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
270 #define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
271 #define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
272 #define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
274 #define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
275 XUSBPS_IXR_UE_MASK | \
276 XUSBPS_IXR_PC_MASK | \
277 XUSBPS_IXR_FRE_MASK | \
278 XUSBPS_IXR_AA_MASK | \
279 XUSBPS_IXR_UR_MASK | \
280 XUSBPS_IXR_SR_MASK | \
281 XUSBPS_IXR_SLE_MASK | \
282 XUSBPS_IXR_ULPI_MASK | \
283 XUSBPS_IXR_HCH_MASK | \
284 XUSBPS_IXR_RCL_MASK | \
285 XUSBPS_IXR_PS_MASK | \
286 XUSBPS_IXR_AS_MASK | \
287 XUSBPS_IXR_NAK_MASK | \
288 XUSBPS_IXR_UA_MASK | \
289 XUSBPS_IXR_UP_MASK | \
290 XUSBPS_IXR_TI0_MASK | \
292 /**< Mask for ALL IRQ types */
296 /** @name USB Mode Register (MODE) bit positions.
299 #define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
300 #define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
301 #define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
302 #define XUSBPS_MODE_CM_HOST_MASK 0x00000003
303 #define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
304 #define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
305 #define XUSBPS_MODE_SDIS_MASK 0x00000010
306 #define XUSBPS_MODE_VALID_MASK 0x0000001F
311 /** @name USB Device Address Register (DEVICEADDR) bit positions.
314 #define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
315 /**< Device Addr Auto Advance */
316 #define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
317 /**< Device Address */
318 #define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
319 /**< Address shift */
320 #define XUSBPS_DEVICEADDR_MAX 127
321 /**< Biggest allowed address */
324 /** @name USB TT Control Register (TTCTRL) bit positions.
327 #define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
331 /** @name USB Burst Size Register (BURSTSIZE) bit posisions.
334 #define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
335 #define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
339 /** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
342 #define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
343 /**< Scheduler Overhead */
344 #define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
345 /**< Scheduler Health Cntr */
346 #define XUSBPS_TXFILL_BURST_MASK 0x003F0000
347 /**< FIFO Burst Threshold */
351 /** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
354 #define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
355 #define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
356 #define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
357 #define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
358 #define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
359 #define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
360 #define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
361 #define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
365 /** @name Port Status Control Register bit positions.
368 #define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
369 #define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
370 #define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
371 #define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
372 #define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
373 #define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
374 #define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
375 #define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
376 #define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
377 #define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
378 #define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
379 #define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
380 #define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
381 #define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
382 #define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
383 #define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
384 #define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
385 #define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
386 #define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
388 #define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
390 #define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
394 /** @name On-The-Go Status Control Register (OTGCSR) bit positions.
397 #define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
398 #define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
399 #define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
401 #define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
402 #define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
404 #define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
405 #define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
407 #define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
409 * Connect Enable Bit */
410 #define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
411 #define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
412 #define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
413 #define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
414 #define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
415 #define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
416 #define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
417 #define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
418 #define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
419 #define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
420 #define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
421 #define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
422 #define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
423 #define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
424 #define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
425 #define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
426 #define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
427 #define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
428 #define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
429 #define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
430 * Interrupt Enable Bit */
431 #define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
434 #define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
435 XUSBPS_OTGSC_AVVIS_MASK | \
436 XUSBPS_OTGSC_ASVIS_MASK | \
437 XUSBPS_OTGSC_BSVIS_MASK | \
438 XUSBPS_OTGSC_BSEIS_MASK | \
439 XUSBPS_OTGSC_1MSS_MASK | \
440 XUSBPS_OTGSC_DPIS_MASK)
441 /** Mask for All IRQ status masks */
443 #define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
444 XUSBPS_OTGSC_AVVIE_MASK | \
445 XUSBPS_OTGSC_ASVIE_MASK | \
446 XUSBPS_OTGSC_BSVIE_MASK | \
447 XUSBPS_OTGSC_BSEE_IEB_MASK | \
448 XUSBPS_OTGSC_1MSE_MASK | \
449 XUSBPS_OTGSC_DPIE_MASK)
450 /** Mask for All IRQ Enable masks */
454 /**< Alignment of the Device Queue Head List BASE. */
455 #define XUSBPS_dQH_BASE_ALIGN 2048
457 /**< Alignment of a Device Queue Head structure. */
458 #define XUSBPS_dQH_ALIGN 64
460 /**< Alignment of a Device Transfer Descriptor structure. */
461 #define XUSBPS_dTD_ALIGN 32
463 /**< Size of one RX buffer for a OUT Transfer Descriptor. */
464 #define XUSBPS_dTD_BUF_SIZE 4096
466 /**< Maximum size of one RX/TX buffer. */
467 #define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
469 /**< Alignment requirement for Transfer Descriptor buffers. */
470 #define XUSBPS_dTD_BUF_ALIGN 4096
473 /**************************** Type Definitions *******************************/
475 /***************** Macros (Inline Functions) Definitions *********************/
477 /****************************************************************************/
480 * This macro reads the given register.
482 * @param BaseAddress is the base address for the USB registers.
483 * @param RegOffset is the register offset to be read.
485 * @return The 32-bit value of the register.
487 * @note C-style signature:
488 * u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
490 *****************************************************************************/
491 #define XUsbPs_ReadReg(BaseAddress, RegOffset) \
492 Xil_In32(BaseAddress + (RegOffset))
495 /****************************************************************************/
498 * This macro writes the given register.
500 * @param BaseAddress is the the base address for the USB registers.
501 * @param RegOffset is the register offset to be written.
502 * @param Data is the the 32-bit value to write to the register.
506 * @note C-style signature:
507 * void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
509 *****************************************************************************/
510 #define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
511 Xil_Out32(BaseAddress + (RegOffset), (Data))
514 /************************** Function Prototypes ******************************/
516 * Perform reset operation to the USB PS interface
518 void XUsbPs_ResetHw(u32 BaseAddress);
519 /************************** Variable Definitions ******************************/
525 #endif /* XUSBPS_L_H */