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32 /*****************************************************************************/
36 * @addtogroup xadcps_v2_0
39 * This file contains interrupt handling API functions of the XADC
42 * The device must be configured at hardware build time to support interrupt
43 * for all the functions in this file to work.
45 * Refer to xadcps.h header file and device specification for more information.
49 * Calling the interrupt functions without including the interrupt component will
50 * result in asserts if asserts are enabled, and will result in a unpredictable
51 * behavior if the asserts are not enabled.
55 * MODIFICATION HISTORY:
57 * Ver Who Date Changes
58 * ----- ----- -------- -----------------------------------------------------
59 * 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
63 ******************************************************************************/
65 /***************************** Include Files *********************************/
69 /************************** Constant Definitions *****************************/
71 /**************************** Type Definitions *******************************/
73 /***************** Macros (Inline Functions) Definitions *********************/
75 /************************** Function Prototypes ******************************/
77 /************************** Variable Definitions *****************************/
80 /****************************************************************************/
83 * This function enables the specified interrupts in the device.
85 * @param InstancePtr is a pointer to the XAdcPs instance.
86 * @param Mask is the bit-mask of the interrupts to be enabled.
87 * Bit positions of 1 will be enabled. Bit positions of 0 will
88 * keep the previous setting. This mask is formed by OR'ing
89 * XADCPS_INTX_* bits defined in xadcps_hw.h.
95 *****************************************************************************/
96 void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
101 * Assert the arguments.
103 Xil_AssertVoid(InstancePtr != NULL);
104 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
107 * Disable the specified interrupts in the IPIER.
109 RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
110 XADCPS_INT_MASK_OFFSET);
111 RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
112 XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
113 XADCPS_INT_MASK_OFFSET,
118 /****************************************************************************/
121 * This function disables the specified interrupts in the device.
123 * @param InstancePtr is a pointer to the XAdcPs instance.
124 * @param Mask is the bit-mask of the interrupts to be disabled.
125 * Bit positions of 1 will be disabled. Bit positions of 0 will
126 * keep the previous setting. This mask is formed by OR'ing
127 * XADCPS_INTX_* bits defined in xadcps_hw.h.
133 *****************************************************************************/
134 void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
139 * Assert the arguments.
141 Xil_AssertVoid(InstancePtr != NULL);
142 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
145 * Enable the specified interrupts in the IPIER.
147 RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
148 XADCPS_INT_MASK_OFFSET);
149 RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
150 XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
151 XADCPS_INT_MASK_OFFSET,
154 /****************************************************************************/
157 * This function returns the enabled interrupts read from the Interrupt Mask
158 * Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
159 * interpret the returned value.
161 * @param InstancePtr is a pointer to the XAdcPs instance.
163 * @return A 32-bit value representing the contents of the I.
167 *****************************************************************************/
168 u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
171 * Assert the arguments.
173 Xil_AssertNonvoid(InstancePtr != NULL);
174 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
177 * Return the value read from the Interrupt Enable Register.
179 return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
180 XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
183 /****************************************************************************/
186 * This function returns the interrupt status read from Interrupt Status
187 * Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
188 * to interpret the returned value.
190 * @param InstancePtr is a pointer to the XAdcPs instance.
192 * @return A 32-bit value representing the contents of the IPISR.
194 * @note The device must be configured at hardware build time to include
195 * interrupt component for this function to work.
197 *****************************************************************************/
198 u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
201 * Assert the arguments.
203 Xil_AssertNonvoid(InstancePtr != NULL);
204 Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
207 * Return the value read from the Interrupt Status register.
209 return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
210 XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
213 /****************************************************************************/
216 * This function clears the specified interrupts in the Interrupt Status
219 * @param InstancePtr is a pointer to the XAdcPs instance.
220 * @param Mask is the bit-mask of the interrupts to be cleared.
221 * Bit positions of 1 will be cleared. Bit positions of 0 will not
222 * change the previous interrupt status. This mask is formed by
223 * OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
229 *****************************************************************************/
230 void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
235 * Assert the arguments.
237 Xil_AssertVoid(InstancePtr != NULL);
238 Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
241 * Clear the specified interrupts in the Interrupt Status register.
243 RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
244 XADCPS_INT_STS_OFFSET);
245 RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
246 XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,