2 /******************************************************************************
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4 * (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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6 * This file contains confidential and proprietary information of Xilinx, Inc.
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7 * and is protected under U.S. and international copyright and other
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8 * intellectual property laws.
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11 * This disclaimer is not a license and does not grant any rights to the
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12 * materials distributed herewith. Except as otherwise provided in a valid
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13 * license issued to you by Xilinx, and to the maximum extent permitted by
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14 * applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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15 * FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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16 * IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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17 * MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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18 * and (2) Xilinx shall not be liable (whether in contract or tort, including
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19 * negligence, or under any other theory of liability) for any loss or damage
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20 * of any kind or nature related to, arising under or in connection with these
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21 * materials, including for any direct, or any indirect, special, incidental,
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22 * or consequential loss or damage (including loss of data, profits, goodwill,
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23 * or any type of loss or damage suffered as a result of any action brought by
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24 * a third party) even if such damage or loss was reasonably foreseeable or
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25 * Xilinx had been advised of the possibility of the same.
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27 * CRITICAL APPLICATIONS
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28 * Xilinx products are not designed or intended to be fail-safe, or for use in
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29 * any application requiring fail-safe performance, such as life-support or
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30 * safety devices or systems, Class III medical devices, nuclear facilities,
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31 * applications related to the deployment of airbags, or any other applications
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32 * that could lead to death, personal injury, or severe property or
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33 * environmental damage (individually and collectively, "Critical
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34 * Applications"). Customer assumes the sole risk and liability of any use of
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35 * Xilinx products in Critical Applications, subject only to applicable laws
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36 * and regulations governing limitations on product liability.
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38 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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41 ******************************************************************************/
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42 /****************************************************************************/
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47 * This file can be included in FSBL code
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48 * to get prototype of ps7_init() function
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51 *****************************************************************************/
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58 //typedef unsigned int u32;
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61 /** do we need to make this name more unique ? **/
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62 //extern u32 ps7_init_data[];
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63 extern unsigned long * ps7_ddr_init_data;
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64 extern unsigned long * ps7_mio_init_data;
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65 extern unsigned long * ps7_pll_init_data;
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66 extern unsigned long * ps7_clock_init_data;
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67 extern unsigned long * ps7_peripherals_init_data;
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71 #define OPCODE_EXIT 0U
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72 #define OPCODE_CLEAR 1U
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73 #define OPCODE_WRITE 2U
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74 #define OPCODE_MASKWRITE 3U
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75 #define OPCODE_MASKPOLL 4U
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76 #define OPCODE_MASKDELAY 5U
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77 #define NEW_PS7_ERR_CODE 1
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79 /* Encode number of arguments in last nibble */
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80 #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
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81 #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
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82 #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
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83 #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
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84 #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
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85 #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
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87 /* Returns codes of PS7_Init */
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88 #define PS7_INIT_SUCCESS (0) // 0 is success in good old C
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89 #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
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90 #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
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91 #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
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92 #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
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93 #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
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96 /* Silicon Versions */
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97 #define PCW_SILICON_VERSION_1 0
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98 #define PCW_SILICON_VERSION_2 1
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99 #define PCW_SILICON_VERSION_3 2
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101 /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
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102 #define PS7_POST_CONFIG
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104 /* Freq of all peripherals */
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106 #define APU_FREQ 666666687
107 #define DDR_FREQ 533333374
108 #define DCI_FREQ 10158731
109 #define QSPI_FREQ 200000000
110 #define SMC_FREQ 10000000
111 #define ENET0_FREQ 25000000
112 #define ENET1_FREQ 10000000
113 #define USB0_FREQ 60000000
114 #define USB1_FREQ 60000000
115 #define SDIO_FREQ 50000000
116 #define UART_FREQ 50000000
117 #define SPI_FREQ 10000000
118 #define I2C_FREQ 111111115
119 #define WDT_FREQ 111111115
120 #define TTC_FREQ 50000000
121 #define CAN_FREQ 23809523
122 #define PCAP_FREQ 200000000
123 #define TPIU_FREQ 200000000
124 #define FPGA0_FREQ 50000000
125 #define FPGA1_FREQ 50000000
126 #define FPGA2_FREQ 50000000
127 #define FPGA3_FREQ 50000000
130 /* For delay calculation using global registers*/
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131 #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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132 #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
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133 #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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134 #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
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136 int ps7_config( unsigned long*);
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138 int ps7_post_config();
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140 char* getPS7MessageInfo(unsigned key);
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142 void perf_start_clock(void);
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143 void perf_disable_clock(void);
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144 void perf_reset_clock(void);
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145 void perf_reset_and_start_timer();
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146 int get_number_of_cycles_for_delay(unsigned int delay);
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