1 /* ----------------------------------------------------------------------------
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2 * ATMEL Microcontroller Software Support
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2008, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 //-----------------------------------------------------------------------------
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32 //-----------------------------------------------------------------------------
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38 #include <utility/trace.h>
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41 #if defined(__ICCARM__)
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42 #include <intrinsics.h>
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46 //-----------------------------------------------------------------------------
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48 //-----------------------------------------------------------------------------
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50 //-----------------------------------------------------------------------------
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52 //-----------------------------------------------------------------------------
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54 #define CP15_RR_BIT 14 // RR bit Replacement strategy for ICache and DCache:
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55 // 0 = Random replacement
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56 // 1 = Round-robin replacement.
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58 #define CP15_V_BIT 13 // V bit Location of exception vectors:
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59 // 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C
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60 // 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C
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62 #define CP15_I_BIT 12 // I bit ICache enable/disable:
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63 // 0 = ICache disabled
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64 // 1 = ICache enabled
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66 #define CP15_R_BIT 9 // R bit ROM protection
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68 #define CP15_S_BIT 8 // S bit System protection
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70 #define CP15_B_BIT 7 // B bit Endianness:
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71 // 0 = Little-endian operation
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72 // 1 = Big-endian operation.
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74 #define CP15_C_BIT 2 // C bit DCache enable/disable:
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75 // 0 = Cache disabled
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76 // 1 = Cache enabled
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78 #define CP15_A_BIT 1 // A bit Alignment fault enable/disable:
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79 // 0 = Data address alignment fault checking disabled
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80 // 1 = Data address alignment fault checking enabled
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82 #define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled.
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87 //-----------------------------------------------------------------------------
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89 //-----------------------------------------------------------------------------
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91 //------------------------------------------------------------------------------
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92 /// Check Instruction Cache
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93 /// \return 0 if I_Cache disable, 1 if I_Cache enable
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94 //------------------------------------------------------------------------------
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95 unsigned int CP15_Is_I_CacheEnabled(void)
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97 unsigned int control;
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99 control = _readControlRegister();
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100 return ((control & (1 << CP15_I_BIT)) != 0);
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103 //------------------------------------------------------------------------------
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104 /// Enable Instruction Cache
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105 //------------------------------------------------------------------------------
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106 void CP15_Enable_I_Cache(void)
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108 unsigned int control;
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110 control = _readControlRegister();
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112 // Check if cache is disabled
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113 if ((control & (1 << CP15_I_BIT)) == 0) {
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115 control |= (1 << CP15_I_BIT);
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116 _writeControlRegister(control);
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117 TRACE_INFO("I cache enabled.\n\r");
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119 #if !defined(OP_BOOTSTRAP_on)
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122 TRACE_INFO("I cache is already enabled.\n\r");
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127 //------------------------------------------------------------------------------
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128 /// Disable Instruction Cache
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129 //------------------------------------------------------------------------------
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130 void CP15_Disable_I_Cache(void)
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132 unsigned int control;
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134 control = _readControlRegister();
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136 // Check if cache is enabled
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137 if ((control & (1 << CP15_I_BIT)) != 0) {
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139 control &= ~(1 << CP15_I_BIT);
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140 _writeControlRegister(control);
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141 TRACE_INFO("I cache disabled.\n\r");
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145 TRACE_INFO("I cache is already disabled.\n\r");
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149 //------------------------------------------------------------------------------
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151 /// \return 0 if MMU disable, 1 if MMU enable
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152 //------------------------------------------------------------------------------
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153 unsigned int CP15_Is_MMUEnabled(void)
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155 unsigned int control;
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157 control = _readControlRegister();
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158 return ((control & (1 << CP15_M_BIT)) != 0);
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161 //------------------------------------------------------------------------------
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163 //------------------------------------------------------------------------------
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164 void CP15_EnableMMU(void)
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166 unsigned int control;
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168 control = _readControlRegister();
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170 // Check if MMU is disabled
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171 if ((control & (1 << CP15_M_BIT)) == 0) {
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173 control |= (1 << CP15_M_BIT);
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174 _writeControlRegister(control);
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175 TRACE_INFO("MMU enabled.\n\r");
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179 TRACE_INFO("MMU is already enabled.\n\r");
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183 //------------------------------------------------------------------------------
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185 //------------------------------------------------------------------------------
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186 void CP15_DisableMMU(void)
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188 unsigned int control;
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190 control = _readControlRegister();
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192 // Check if MMU is enabled
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193 if ((control & (1 << CP15_M_BIT)) != 0) {
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195 control &= ~(1 << CP15_M_BIT);
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196 control &= ~(1 << CP15_C_BIT);
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197 _writeControlRegister(control);
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198 TRACE_INFO("MMU disabled.\n\r");
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202 TRACE_INFO("MMU is already disabled.\n\r");
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206 //------------------------------------------------------------------------------
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208 /// \return 0 if D_Cache disable, 1 if D_Cache enable (with MMU of course)
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209 //------------------------------------------------------------------------------
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210 unsigned int CP15_Is_DCacheEnabled(void)
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212 unsigned int control;
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214 control = _readControlRegister();
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215 return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0);
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218 //------------------------------------------------------------------------------
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219 /// Enable Data Cache
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220 //------------------------------------------------------------------------------
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221 void CP15_Enable_D_Cache(void)
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223 unsigned int control;
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225 control = _readControlRegister();
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227 if( !CP15_Is_MMUEnabled() ) {
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228 TRACE_ERROR("Do nothing: MMU not enabled\n\r");
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231 // Check if cache is disabled
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232 if ((control & (1 << CP15_C_BIT)) == 0) {
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234 control |= (1 << CP15_C_BIT);
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235 _writeControlRegister(control);
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236 TRACE_INFO("D cache enabled.\n\r");
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240 TRACE_INFO("D cache is already enabled.\n\r");
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245 //------------------------------------------------------------------------------
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246 /// Disable Data Cache
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247 //------------------------------------------------------------------------------
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248 void CP15_Disable_D_Cache(void)
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250 unsigned int control;
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252 control = _readControlRegister();
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254 // Check if cache is enabled
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255 if ((control & (1 << CP15_C_BIT)) != 0) {
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257 control &= ~(1 << CP15_C_BIT);
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258 _writeControlRegister(control);
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259 TRACE_INFO("D cache disabled.\n\r");
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263 TRACE_INFO("D cache is already disabled.\n\r");
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267 #endif // CP15_PRESENT
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