git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_ATSAM3X_Atmel_Studio/src/asf/common/services/clock/sam3x/genclk.h

   1 /**\r
   2  * \file\r
   3  *\r
   4  * \brief Chip-specific generic clock management.\r
   5  *\r
   6  * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.s\r
   7  *\r
   8  * \asf_license_start\r
   9  *\r
  10  * \page License\r
  11  *\r
  12  * Redistribution and use in source and binary forms, with or without\r
  13  * modification, are permitted provided that the following conditions are met:\r
  14  *\r
  15  * 1. Redistributions of source code must retain the above copyright notice,\r
  16  *    this list of conditions and the following disclaimer.\r
  17  *\r
  18  * 2. Redistributions in binary form must reproduce the above copyright notice,\r
  19  *    this list of conditions and the following disclaimer in the documentation\r
  20  *    and/or other materials provided with the distribution.\r
  21  *\r
  22  * 3. The name of Atmel may not be used to endorse or promote products derived\r
  23  *    from this software without specific prior written permission.\r
  24  *\r
  25  * 4. This software may only be redistributed and used in connection with an\r
  26  *    Atmel microcontroller product.\r
  27  *\r
  28  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
  29  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
  30  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
  31  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
  32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
  36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
  37  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
  38  * POSSIBILITY OF SUCH DAMAGE.\r
  39  *\r
  40  * \asf_license_stop\r
  41  *\r
  42  */\r
  43 \r
  44 #ifndef CHIP_GENCLK_H_INCLUDED\r
  45 #define CHIP_GENCLK_H_INCLUDED\r
  46 \r
  47 #include <osc.h>\r
  48 #include <pll.h>\r
  49 \r
  50 /// @cond 0\r
  51 /**INDENT-OFF**/\r
  52 #ifdef __cplusplus\r
  53 extern "C" {\r
  54 #endif\r
  55 /**INDENT-ON**/\r
  56 /// @endcond\r
  57 \r
  58 /**\r
  59  * \weakgroup genclk_group\r
  60  * @{\r
  61  */\r
  62 \r
  63 //! \name Programmable Clock Identifiers (PCK)\r
  64 //@{\r
  65 #define GENCLK_PCK_0                    0                                               //!< PCK0 ID\r
  66 #define GENCLK_PCK_1                    1                                               //!< PCK1 ID\r
  67 #define GENCLK_PCK_2                    2                                               //!< PCK2 ID\r
  68 //@}\r
  69 \r
  70 //! \name Programmable Clock Sources (PCK)\r
  71 //@{\r
  72 \r
  73 enum genclk_source {\r
  74         GENCLK_PCK_SRC_SLCK_RC                  =       0,      //!< Internal 32kHz RC oscillator as PCK source clock\r
  75         GENCLK_PCK_SRC_SLCK_XTAL                =       1,      //!< External 32kHz crystal oscillator as PCK source clock\r
  76         GENCLK_PCK_SRC_SLCK_BYPASS              =       2,      //!< External 32kHz bypass oscillator as PCK source clock\r
  77         GENCLK_PCK_SRC_MAINCK_4M_RC             =       3,      //!< Internal 4MHz RC oscillator as PCK source clock\r
  78         GENCLK_PCK_SRC_MAINCK_8M_RC             =       4,      //!< Internal 8MHz RC oscillator as PCK source clock\r
  79         GENCLK_PCK_SRC_MAINCK_12M_RC    =       5,      //!< Internal 12MHz RC oscillator as PCK source clock\r
  80         GENCLK_PCK_SRC_MAINCK_XTAL              =       6,      //!< External crystal oscillator as PCK source clock\r
  81         GENCLK_PCK_SRC_MAINCK_BYPASS    =       7,      //!< External bypass oscillator as PCK source clock\r
  82         GENCLK_PCK_SRC_PLLACK                   =       8,      //!< Use PLLACK as PCK source clock\r
  83         GENCLK_PCK_SRC_PLLBCK                   =       9,      //!< Use PLLBCK as PCK source clock\r
  84 };\r
  85 \r
  86 //@}\r
  87 \r
  88 //! \name Programmable Clock Prescalers (PCK)\r
  89 //@{\r
  90 \r
  91 enum genclk_divider {\r
  92         GENCLK_PCK_PRES_1       =       PMC_PCK_PRES_CLK_1,             //!< Set PCK clock prescaler to 1\r
  93         GENCLK_PCK_PRES_2       =       PMC_PCK_PRES_CLK_2,             //!< Set PCK clock prescaler to 2\r
  94         GENCLK_PCK_PRES_4       =       PMC_PCK_PRES_CLK_4,             //!< Set PCK clock prescaler to 4\r
  95         GENCLK_PCK_PRES_8       =       PMC_PCK_PRES_CLK_8,             //!< Set PCK clock prescaler to 8\r
  96         GENCLK_PCK_PRES_16      =       PMC_PCK_PRES_CLK_16,    //!< Set PCK clock prescaler to 16\r
  97         GENCLK_PCK_PRES_32      =       PMC_PCK_PRES_CLK_32,    //!< Set PCK clock prescaler to 32\r
  98         GENCLK_PCK_PRES_64      =       PMC_PCK_PRES_CLK_64,    //!< Set PCK clock prescaler to 64\r
  99 };\r
 100 \r
 101 //@}\r
 102 \r
 103 struct genclk_config {\r
 104         uint32_t ctrl;\r
 105 };\r
 106 \r
 107 static inline void genclk_config_defaults(struct genclk_config *p_cfg,\r
 108                 uint32_t ul_id)\r
 109 {\r
 110         ul_id = ul_id;\r
 111         p_cfg->ctrl = 0;\r
 112 }\r
 113 \r
 114 static inline void genclk_config_read(struct genclk_config *p_cfg,\r
 115                 uint32_t ul_id)\r
 116 {\r
 117         p_cfg->ctrl = PMC->PMC_PCK[ul_id];\r
 118 }\r
 119 \r
 120 static inline void genclk_config_write(const struct genclk_config *p_cfg,\r
 121                 uint32_t ul_id)\r
 122 {\r
 123         PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
 124 }\r
 125 \r
 126 //! \name Programmable Clock Source and Prescaler configuration\r
 127 //@{\r
 128 \r
 129 static inline void genclk_config_set_source(struct genclk_config *p_cfg,\r
 130                 enum genclk_source e_src)\r
 131 {\r
 132         p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);\r
 133 \r
 134         switch (e_src) {\r
 135         case GENCLK_PCK_SRC_SLCK_RC:\r
 136         case GENCLK_PCK_SRC_SLCK_XTAL:\r
 137         case GENCLK_PCK_SRC_SLCK_BYPASS:\r
 138                 p_cfg->ctrl |= (PMC_MCKR_CSS_SLOW_CLK);\r
 139                 break;\r
 140 \r
 141         case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
 142         case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
 143         case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
 144         case GENCLK_PCK_SRC_MAINCK_XTAL:\r
 145         case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
 146                 p_cfg->ctrl |= (PMC_MCKR_CSS_MAIN_CLK);\r
 147                 break;\r
 148 \r
 149         case GENCLK_PCK_SRC_PLLACK:\r
 150                 p_cfg->ctrl |= (PMC_MCKR_CSS_PLLA_CLK);\r
 151                 break;\r
 152 \r
 153         case GENCLK_PCK_SRC_PLLBCK:\r
 154                 p_cfg->ctrl |= (PMC_MCKR_CSS_UPLL_CLK);\r
 155                 break;\r
 156         }\r
 157 }\r
 158 \r
 159 static inline void genclk_config_set_divider(struct genclk_config *p_cfg,\r
 160                 uint32_t e_divider)\r
 161 {\r
 162         p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;\r
 163         p_cfg->ctrl |= e_divider;       \r
 164 }\r
 165 \r
 166 //@}\r
 167 \r
 168 static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)\r
 169 {\r
 170         PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
 171         pmc_enable_pck(ul_id);\r
 172 }\r
 173 \r
 174 static inline void genclk_disable(uint32_t ul_id)\r
 175 {\r
 176         pmc_disable_pck(ul_id);\r
 177 }\r
 178 \r
 179 static inline void genclk_enable_source(enum genclk_source e_src)\r
 180 {\r
 181         switch (e_src) {\r
 182         case GENCLK_PCK_SRC_SLCK_RC:\r
 183                 if (!osc_is_ready(OSC_SLCK_32K_RC)) {\r
 184                         osc_enable(OSC_SLCK_32K_RC);\r
 185                         osc_wait_ready(OSC_SLCK_32K_RC);\r
 186                 }               \r
 187                 break;\r
 188         \r
 189         case GENCLK_PCK_SRC_SLCK_XTAL:\r
 190                 if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {\r
 191                         osc_enable(OSC_SLCK_32K_XTAL);\r
 192                         osc_wait_ready(OSC_SLCK_32K_XTAL);\r
 193                 }\r
 194                 break;\r
 195                 \r
 196         case GENCLK_PCK_SRC_SLCK_BYPASS:\r
 197                 if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {\r
 198                         osc_enable(OSC_SLCK_32K_BYPASS);\r
 199                         osc_wait_ready(OSC_SLCK_32K_BYPASS);            \r
 200                 }               \r
 201                 break;\r
 202         \r
 203     case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
 204                 if (!osc_is_ready(OSC_MAINCK_4M_RC)) {\r
 205                         osc_enable(OSC_MAINCK_4M_RC);\r
 206                         osc_wait_ready(OSC_MAINCK_4M_RC);               \r
 207                 }               \r
 208                 break;\r
 209 \r
 210     case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
 211                 if (!osc_is_ready(OSC_MAINCK_8M_RC)) {\r
 212                         osc_enable(OSC_MAINCK_8M_RC);\r
 213                         osc_wait_ready(OSC_MAINCK_8M_RC);               \r
 214                 }               \r
 215                 break;\r
 216 \r
 217     case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
 218                 if (!osc_is_ready(OSC_MAINCK_12M_RC)) {\r
 219                         osc_enable(OSC_MAINCK_12M_RC);\r
 220                         osc_wait_ready(OSC_MAINCK_12M_RC);              \r
 221                 }               \r
 222                 break;\r
 223 \r
 224     case GENCLK_PCK_SRC_MAINCK_XTAL:\r
 225                 if (!osc_is_ready(OSC_MAINCK_XTAL)) {\r
 226                         osc_enable(OSC_MAINCK_XTAL);\r
 227                         osc_wait_ready(OSC_MAINCK_XTAL);                \r
 228                 }               \r
 229                 break;\r
 230 \r
 231     case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
 232                 if (!osc_is_ready(OSC_MAINCK_BYPASS)) {\r
 233                         osc_enable(OSC_MAINCK_BYPASS);\r
 234                         osc_wait_ready(OSC_MAINCK_BYPASS);              \r
 235                 }               \r
 236                 break;\r
 237 \r
 238 #ifdef CONFIG_PLL0_SOURCE\r
 239         case GENCLK_PCK_SRC_PLLACK:\r
 240                 pll_enable_config_defaults(0);          \r
 241                 break;  \r
 242 #endif\r
 243 \r
 244 #ifdef CONFIG_PLL1_SOURCE\r
 245         case GENCLK_PCK_SRC_PLLBCK:\r
 246                 pll_enable_config_defaults(1);          \r
 247                 break;  \r
 248 #endif  \r
 249 \r
 250         default:\r
 251                 Assert(false);\r
 252                 break;\r
 253         }\r
 254 }\r
 255 \r
 256 //! @}\r
 257 \r
 258 /// @cond 0\r
 259 /**INDENT-OFF**/\r
 260 #ifdef __cplusplus\r
 261 }\r
 262 #endif\r
 263 /**INDENT-ON**/\r
 264 /// @endcond\r
 265 \r
 266 #endif /* CHIP_GENCLK_H_INCLUDED */\r