4 * \brief Chip-specific generic clock management.
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6 * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.s
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 #ifndef CHIP_GENCLK_H_INCLUDED
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45 #define CHIP_GENCLK_H_INCLUDED
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59 * \weakgroup genclk_group
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63 //! \name Programmable Clock Identifiers (PCK)
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65 #define GENCLK_PCK_0 0 //!< PCK0 ID
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66 #define GENCLK_PCK_1 1 //!< PCK1 ID
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67 #define GENCLK_PCK_2 2 //!< PCK2 ID
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70 //! \name Programmable Clock Sources (PCK)
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73 enum genclk_source {
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74 GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
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75 GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
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76 GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
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77 GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
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78 GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
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79 GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
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80 GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
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81 GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
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82 GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
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83 GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
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88 //! \name Programmable Clock Prescalers (PCK)
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91 enum genclk_divider {
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92 GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
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93 GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
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94 GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
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95 GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
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96 GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
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97 GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
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98 GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
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103 struct genclk_config {
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107 static inline void genclk_config_defaults(struct genclk_config *p_cfg,
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114 static inline void genclk_config_read(struct genclk_config *p_cfg,
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117 p_cfg->ctrl = PMC->PMC_PCK[ul_id];
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120 static inline void genclk_config_write(const struct genclk_config *p_cfg,
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123 PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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126 //! \name Programmable Clock Source and Prescaler configuration
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129 static inline void genclk_config_set_source(struct genclk_config *p_cfg,
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130 enum genclk_source e_src)
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132 p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
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135 case GENCLK_PCK_SRC_SLCK_RC:
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136 case GENCLK_PCK_SRC_SLCK_XTAL:
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137 case GENCLK_PCK_SRC_SLCK_BYPASS:
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138 p_cfg->ctrl |= (PMC_MCKR_CSS_SLOW_CLK);
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141 case GENCLK_PCK_SRC_MAINCK_4M_RC:
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142 case GENCLK_PCK_SRC_MAINCK_8M_RC:
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143 case GENCLK_PCK_SRC_MAINCK_12M_RC:
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144 case GENCLK_PCK_SRC_MAINCK_XTAL:
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145 case GENCLK_PCK_SRC_MAINCK_BYPASS:
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146 p_cfg->ctrl |= (PMC_MCKR_CSS_MAIN_CLK);
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149 case GENCLK_PCK_SRC_PLLACK:
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150 p_cfg->ctrl |= (PMC_MCKR_CSS_PLLA_CLK);
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153 case GENCLK_PCK_SRC_PLLBCK:
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154 p_cfg->ctrl |= (PMC_MCKR_CSS_UPLL_CLK);
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159 static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
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160 uint32_t e_divider)
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162 p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
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163 p_cfg->ctrl |= e_divider;
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168 static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
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170 PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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171 pmc_enable_pck(ul_id);
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174 static inline void genclk_disable(uint32_t ul_id)
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176 pmc_disable_pck(ul_id);
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179 static inline void genclk_enable_source(enum genclk_source e_src)
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182 case GENCLK_PCK_SRC_SLCK_RC:
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183 if (!osc_is_ready(OSC_SLCK_32K_RC)) {
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184 osc_enable(OSC_SLCK_32K_RC);
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185 osc_wait_ready(OSC_SLCK_32K_RC);
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189 case GENCLK_PCK_SRC_SLCK_XTAL:
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190 if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
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191 osc_enable(OSC_SLCK_32K_XTAL);
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192 osc_wait_ready(OSC_SLCK_32K_XTAL);
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196 case GENCLK_PCK_SRC_SLCK_BYPASS:
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197 if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
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198 osc_enable(OSC_SLCK_32K_BYPASS);
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199 osc_wait_ready(OSC_SLCK_32K_BYPASS);
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203 case GENCLK_PCK_SRC_MAINCK_4M_RC:
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204 if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
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205 osc_enable(OSC_MAINCK_4M_RC);
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206 osc_wait_ready(OSC_MAINCK_4M_RC);
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210 case GENCLK_PCK_SRC_MAINCK_8M_RC:
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211 if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
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212 osc_enable(OSC_MAINCK_8M_RC);
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213 osc_wait_ready(OSC_MAINCK_8M_RC);
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217 case GENCLK_PCK_SRC_MAINCK_12M_RC:
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218 if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
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219 osc_enable(OSC_MAINCK_12M_RC);
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220 osc_wait_ready(OSC_MAINCK_12M_RC);
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224 case GENCLK_PCK_SRC_MAINCK_XTAL:
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225 if (!osc_is_ready(OSC_MAINCK_XTAL)) {
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226 osc_enable(OSC_MAINCK_XTAL);
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227 osc_wait_ready(OSC_MAINCK_XTAL);
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231 case GENCLK_PCK_SRC_MAINCK_BYPASS:
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232 if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
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233 osc_enable(OSC_MAINCK_BYPASS);
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234 osc_wait_ready(OSC_MAINCK_BYPASS);
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238 #ifdef CONFIG_PLL0_SOURCE
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239 case GENCLK_PCK_SRC_PLLACK:
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240 pll_enable_config_defaults(0);
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244 #ifdef CONFIG_PLL1_SOURCE
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245 case GENCLK_PCK_SRC_PLLBCK:
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246 pll_enable_config_defaults(1);
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266 #endif /* CHIP_GENCLK_H_INCLUDED */
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