4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM3XA_PIOD_INSTANCE_
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43 #define _SAM3XA_PIOD_INSTANCE_
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45 /* ========== Register definition for PIOD peripheral ========== */
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46 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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47 #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
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48 #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
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49 #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
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50 #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
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51 #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
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52 #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */
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53 #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
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54 #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
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55 #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
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56 #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
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57 #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
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58 #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
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59 #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
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60 #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
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61 #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
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62 #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
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63 #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
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64 #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
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65 #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
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66 #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
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67 #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
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68 #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
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69 #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
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70 #define REG_PIOD_ABSR (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
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71 #define REG_PIOD_SCIFSR (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
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72 #define REG_PIOD_DIFSR (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
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73 #define REG_PIOD_IFDGSR (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
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74 #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
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75 #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
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76 #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
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77 #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
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78 #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
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79 #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
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80 #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
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81 #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
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82 #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
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83 #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
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84 #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
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85 #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
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86 #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
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87 #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */
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88 #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
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89 #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
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91 #define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
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92 #define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
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93 #define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
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94 #define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
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95 #define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
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96 #define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
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97 #define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
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98 #define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
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99 #define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
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100 #define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
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101 #define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
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102 #define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
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103 #define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
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104 #define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
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105 #define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
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106 #define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
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107 #define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
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108 #define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
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109 #define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
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110 #define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
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111 #define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
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112 #define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
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113 #define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
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114 #define REG_PIOD_ABSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
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115 #define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
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116 #define REG_PIOD_DIFSR (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
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117 #define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
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118 #define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
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119 #define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
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120 #define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
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121 #define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
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122 #define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
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123 #define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
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124 #define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
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125 #define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
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126 #define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
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127 #define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
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128 #define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
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129 #define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
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130 #define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
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131 #define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
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132 #define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
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133 #define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
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134 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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136 #endif /* _SAM3XA_PIOD_INSTANCE_ */
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