4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
\r
10 * Redistribution and use in source and binary forms, with or without
\r
11 * modification, are permitted provided that the following conditions are met:
\r
13 * 1. Redistributions of source code must retain the above copyright notice,
\r
14 * this list of conditions and the following disclaimer.
\r
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
17 * this list of conditions and the following disclaimer in the documentation
\r
18 * and/or other materials provided with the distribution.
\r
20 * 3. The name of Atmel may not be used to endorse or promote products derived
\r
21 * from this software without specific prior written permission.
\r
23 * 4. This software may only be redistributed and used in connection with an
\r
24 * Atmel microcontroller product.
\r
26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
\r
27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
\r
29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
\r
30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
\r
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
\r
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
\r
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\r
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\r
36 * POSSIBILITY OF SUCH DAMAGE.
\r
42 #ifndef _SAM3XA_PWM_INSTANCE_
\r
43 #define _SAM3XA_PWM_INSTANCE_
\r
45 /* ========== Register definition for PWM peripheral ========== */
\r
46 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
47 #define REG_PWM_CLK (0x40094000U) /**< \brief (PWM) PWM Clock Register */
\r
48 #define REG_PWM_ENA (0x40094004U) /**< \brief (PWM) PWM Enable Register */
\r
49 #define REG_PWM_DIS (0x40094008U) /**< \brief (PWM) PWM Disable Register */
\r
50 #define REG_PWM_SR (0x4009400CU) /**< \brief (PWM) PWM Status Register */
\r
51 #define REG_PWM_IER1 (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
\r
52 #define REG_PWM_IDR1 (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
\r
53 #define REG_PWM_IMR1 (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
\r
54 #define REG_PWM_ISR1 (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
\r
55 #define REG_PWM_SCM (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
\r
56 #define REG_PWM_SCUC (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
\r
57 #define REG_PWM_SCUP (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
\r
58 #define REG_PWM_SCUPUPD (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
\r
59 #define REG_PWM_IER2 (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
\r
60 #define REG_PWM_IDR2 (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
\r
61 #define REG_PWM_IMR2 (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
\r
62 #define REG_PWM_ISR2 (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
\r
63 #define REG_PWM_OOV (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
\r
64 #define REG_PWM_OS (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
\r
65 #define REG_PWM_OSS (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
\r
66 #define REG_PWM_OSC (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
\r
67 #define REG_PWM_OSSUPD (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
\r
68 #define REG_PWM_OSCUPD (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
\r
69 #define REG_PWM_FMR (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
\r
70 #define REG_PWM_FSR (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
\r
71 #define REG_PWM_FCR (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
\r
72 #define REG_PWM_FPV (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
\r
73 #define REG_PWM_FPE1 (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
\r
74 #define REG_PWM_FPE2 (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
\r
75 #define REG_PWM_ELMR (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
\r
76 #define REG_PWM_SMMR (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
\r
77 #define REG_PWM_WPCR (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
\r
78 #define REG_PWM_WPSR (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
\r
79 #define REG_PWM_TPR (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
\r
80 #define REG_PWM_TCR (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
\r
81 #define REG_PWM_TNPR (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
\r
82 #define REG_PWM_TNCR (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
\r
83 #define REG_PWM_PTCR (0x40094120U) /**< \brief (PWM) Transfer Control Register */
\r
84 #define REG_PWM_PTSR (0x40094124U) /**< \brief (PWM) Transfer Status Register */
\r
85 #define REG_PWM_CMPV0 (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
\r
86 #define REG_PWM_CMPVUPD0 (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
\r
87 #define REG_PWM_CMPM0 (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
\r
88 #define REG_PWM_CMPMUPD0 (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
\r
89 #define REG_PWM_CMPV1 (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
\r
90 #define REG_PWM_CMPVUPD1 (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
\r
91 #define REG_PWM_CMPM1 (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
\r
92 #define REG_PWM_CMPMUPD1 (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
\r
93 #define REG_PWM_CMPV2 (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
\r
94 #define REG_PWM_CMPVUPD2 (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
\r
95 #define REG_PWM_CMPM2 (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
\r
96 #define REG_PWM_CMPMUPD2 (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
\r
97 #define REG_PWM_CMPV3 (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
\r
98 #define REG_PWM_CMPVUPD3 (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
\r
99 #define REG_PWM_CMPM3 (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
\r
100 #define REG_PWM_CMPMUPD3 (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
\r
101 #define REG_PWM_CMPV4 (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
\r
102 #define REG_PWM_CMPVUPD4 (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
\r
103 #define REG_PWM_CMPM4 (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
\r
104 #define REG_PWM_CMPMUPD4 (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
\r
105 #define REG_PWM_CMPV5 (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
\r
106 #define REG_PWM_CMPVUPD5 (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
\r
107 #define REG_PWM_CMPM5 (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
\r
108 #define REG_PWM_CMPMUPD5 (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
\r
109 #define REG_PWM_CMPV6 (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
\r
110 #define REG_PWM_CMPVUPD6 (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
\r
111 #define REG_PWM_CMPM6 (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
\r
112 #define REG_PWM_CMPMUPD6 (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
\r
113 #define REG_PWM_CMPV7 (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
\r
114 #define REG_PWM_CMPVUPD7 (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
\r
115 #define REG_PWM_CMPM7 (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
\r
116 #define REG_PWM_CMPMUPD7 (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
\r
117 #define REG_PWM_CMR0 (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
\r
118 #define REG_PWM_CDTY0 (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
\r
119 #define REG_PWM_CDTYUPD0 (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
\r
120 #define REG_PWM_CPRD0 (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
\r
121 #define REG_PWM_CPRDUPD0 (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
\r
122 #define REG_PWM_CCNT0 (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
\r
123 #define REG_PWM_DT0 (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
\r
124 #define REG_PWM_DTUPD0 (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
\r
125 #define REG_PWM_CMR1 (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
\r
126 #define REG_PWM_CDTY1 (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
\r
127 #define REG_PWM_CDTYUPD1 (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
\r
128 #define REG_PWM_CPRD1 (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
\r
129 #define REG_PWM_CPRDUPD1 (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
\r
130 #define REG_PWM_CCNT1 (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
\r
131 #define REG_PWM_DT1 (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
\r
132 #define REG_PWM_DTUPD1 (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
\r
133 #define REG_PWM_CMR2 (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
\r
134 #define REG_PWM_CDTY2 (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
\r
135 #define REG_PWM_CDTYUPD2 (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
\r
136 #define REG_PWM_CPRD2 (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
\r
137 #define REG_PWM_CPRDUPD2 (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
\r
138 #define REG_PWM_CCNT2 (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
\r
139 #define REG_PWM_DT2 (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
\r
140 #define REG_PWM_DTUPD2 (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
\r
141 #define REG_PWM_CMR3 (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
\r
142 #define REG_PWM_CDTY3 (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
\r
143 #define REG_PWM_CDTYUPD3 (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
\r
144 #define REG_PWM_CPRD3 (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
\r
145 #define REG_PWM_CPRDUPD3 (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
\r
146 #define REG_PWM_CCNT3 (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
\r
147 #define REG_PWM_DT3 (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
\r
148 #define REG_PWM_DTUPD3 (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
\r
149 #define REG_PWM_CMR4 (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
\r
150 #define REG_PWM_CDTY4 (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
\r
151 #define REG_PWM_CDTYUPD4 (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
\r
152 #define REG_PWM_CPRD4 (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
\r
153 #define REG_PWM_CPRDUPD4 (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
\r
154 #define REG_PWM_CCNT4 (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
\r
155 #define REG_PWM_DT4 (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
\r
156 #define REG_PWM_DTUPD4 (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
\r
157 #define REG_PWM_CMR5 (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
\r
158 #define REG_PWM_CDTY5 (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
\r
159 #define REG_PWM_CDTYUPD5 (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
\r
160 #define REG_PWM_CPRD5 (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
\r
161 #define REG_PWM_CPRDUPD5 (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
\r
162 #define REG_PWM_CCNT5 (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
\r
163 #define REG_PWM_DT5 (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
\r
164 #define REG_PWM_DTUPD5 (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
\r
165 #define REG_PWM_CMR6 (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
\r
166 #define REG_PWM_CDTY6 (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
\r
167 #define REG_PWM_CDTYUPD6 (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
\r
168 #define REG_PWM_CPRD6 (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
\r
169 #define REG_PWM_CPRDUPD6 (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
\r
170 #define REG_PWM_CCNT6 (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
\r
171 #define REG_PWM_DT6 (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
\r
172 #define REG_PWM_DTUPD6 (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
\r
173 #define REG_PWM_CMR7 (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
\r
174 #define REG_PWM_CDTY7 (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
\r
175 #define REG_PWM_CDTYUPD7 (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
\r
176 #define REG_PWM_CPRD7 (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
\r
177 #define REG_PWM_CPRDUPD7 (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
\r
178 #define REG_PWM_CCNT7 (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
\r
179 #define REG_PWM_DT7 (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
\r
180 #define REG_PWM_DTUPD7 (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
\r
182 #define REG_PWM_CLK (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */
\r
183 #define REG_PWM_ENA (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */
\r
184 #define REG_PWM_DIS (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */
\r
185 #define REG_PWM_SR (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */
\r
186 #define REG_PWM_IER1 (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
\r
187 #define REG_PWM_IDR1 (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
\r
188 #define REG_PWM_IMR1 (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
\r
189 #define REG_PWM_ISR1 (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
\r
190 #define REG_PWM_SCM (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
\r
191 #define REG_PWM_SCUC (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
\r
192 #define REG_PWM_SCUP (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
\r
193 #define REG_PWM_SCUPUPD (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
\r
194 #define REG_PWM_IER2 (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
\r
195 #define REG_PWM_IDR2 (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
\r
196 #define REG_PWM_IMR2 (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
\r
197 #define REG_PWM_ISR2 (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
\r
198 #define REG_PWM_OOV (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
\r
199 #define REG_PWM_OS (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
\r
200 #define REG_PWM_OSS (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
\r
201 #define REG_PWM_OSC (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
\r
202 #define REG_PWM_OSSUPD (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
\r
203 #define REG_PWM_OSCUPD (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
\r
204 #define REG_PWM_FMR (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
\r
205 #define REG_PWM_FSR (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
\r
206 #define REG_PWM_FCR (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
\r
207 #define REG_PWM_FPV (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
\r
208 #define REG_PWM_FPE1 (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
\r
209 #define REG_PWM_FPE2 (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
\r
210 #define REG_PWM_ELMR (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
\r
211 #define REG_PWM_SMMR (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
\r
212 #define REG_PWM_WPCR (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
\r
213 #define REG_PWM_WPSR (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
\r
214 #define REG_PWM_TPR (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
\r
215 #define REG_PWM_TCR (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
\r
216 #define REG_PWM_TNPR (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
\r
217 #define REG_PWM_TNCR (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
\r
218 #define REG_PWM_PTCR (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */
\r
219 #define REG_PWM_PTSR (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */
\r
220 #define REG_PWM_CMPV0 (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
\r
221 #define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
\r
222 #define REG_PWM_CMPM0 (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
\r
223 #define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
\r
224 #define REG_PWM_CMPV1 (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
\r
225 #define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
\r
226 #define REG_PWM_CMPM1 (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
\r
227 #define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
\r
228 #define REG_PWM_CMPV2 (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
\r
229 #define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
\r
230 #define REG_PWM_CMPM2 (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
\r
231 #define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
\r
232 #define REG_PWM_CMPV3 (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
\r
233 #define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
\r
234 #define REG_PWM_CMPM3 (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
\r
235 #define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
\r
236 #define REG_PWM_CMPV4 (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
\r
237 #define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
\r
238 #define REG_PWM_CMPM4 (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
\r
239 #define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
\r
240 #define REG_PWM_CMPV5 (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
\r
241 #define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
\r
242 #define REG_PWM_CMPM5 (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
\r
243 #define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
\r
244 #define REG_PWM_CMPV6 (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
\r
245 #define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
\r
246 #define REG_PWM_CMPM6 (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
\r
247 #define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
\r
248 #define REG_PWM_CMPV7 (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
\r
249 #define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
\r
250 #define REG_PWM_CMPM7 (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
\r
251 #define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
\r
252 #define REG_PWM_CMR0 (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
\r
253 #define REG_PWM_CDTY0 (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
\r
254 #define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
\r
255 #define REG_PWM_CPRD0 (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
\r
256 #define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
\r
257 #define REG_PWM_CCNT0 (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
\r
258 #define REG_PWM_DT0 (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
\r
259 #define REG_PWM_DTUPD0 (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
\r
260 #define REG_PWM_CMR1 (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
\r
261 #define REG_PWM_CDTY1 (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
\r
262 #define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
\r
263 #define REG_PWM_CPRD1 (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
\r
264 #define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
\r
265 #define REG_PWM_CCNT1 (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
\r
266 #define REG_PWM_DT1 (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
\r
267 #define REG_PWM_DTUPD1 (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
\r
268 #define REG_PWM_CMR2 (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
\r
269 #define REG_PWM_CDTY2 (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
\r
270 #define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
\r
271 #define REG_PWM_CPRD2 (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
\r
272 #define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
\r
273 #define REG_PWM_CCNT2 (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
\r
274 #define REG_PWM_DT2 (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
\r
275 #define REG_PWM_DTUPD2 (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
\r
276 #define REG_PWM_CMR3 (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
\r
277 #define REG_PWM_CDTY3 (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
\r
278 #define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
\r
279 #define REG_PWM_CPRD3 (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
\r
280 #define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
\r
281 #define REG_PWM_CCNT3 (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
\r
282 #define REG_PWM_DT3 (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
\r
283 #define REG_PWM_DTUPD3 (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
\r
284 #define REG_PWM_CMR4 (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
\r
285 #define REG_PWM_CDTY4 (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
\r
286 #define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
\r
287 #define REG_PWM_CPRD4 (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
\r
288 #define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
\r
289 #define REG_PWM_CCNT4 (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
\r
290 #define REG_PWM_DT4 (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
\r
291 #define REG_PWM_DTUPD4 (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
\r
292 #define REG_PWM_CMR5 (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
\r
293 #define REG_PWM_CDTY5 (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
\r
294 #define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
\r
295 #define REG_PWM_CPRD5 (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
\r
296 #define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
\r
297 #define REG_PWM_CCNT5 (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
\r
298 #define REG_PWM_DT5 (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
\r
299 #define REG_PWM_DTUPD5 (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
\r
300 #define REG_PWM_CMR6 (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
\r
301 #define REG_PWM_CDTY6 (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
\r
302 #define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
\r
303 #define REG_PWM_CPRD6 (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
\r
304 #define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
\r
305 #define REG_PWM_CCNT6 (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
\r
306 #define REG_PWM_DT6 (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
\r
307 #define REG_PWM_DTUPD6 (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
\r
308 #define REG_PWM_CMR7 (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
\r
309 #define REG_PWM_CDTY7 (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
\r
310 #define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
\r
311 #define REG_PWM_CPRD7 (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
\r
312 #define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
\r
313 #define REG_PWM_CCNT7 (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
\r
314 #define REG_PWM_DT7 (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
\r
315 #define REG_PWM_DTUPD7 (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
\r
316 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
318 #endif /* _SAM3XA_PWM_INSTANCE_ */
\r