4 * Copyright (c) 2012 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 #ifndef _SAM3XA_USART3_INSTANCE_
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43 #define _SAM3XA_USART3_INSTANCE_
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45 /* ========== Register definition for USART3 peripheral ========== */
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46 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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47 #define REG_USART3_CR (0x400A4000U) /**< \brief (USART3) Control Register */
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48 #define REG_USART3_MR (0x400A4004U) /**< \brief (USART3) Mode Register */
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49 #define REG_USART3_IER (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
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50 #define REG_USART3_IDR (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
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51 #define REG_USART3_IMR (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
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52 #define REG_USART3_CSR (0x400A4014U) /**< \brief (USART3) Channel Status Register */
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53 #define REG_USART3_RHR (0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
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54 #define REG_USART3_THR (0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
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55 #define REG_USART3_BRGR (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
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56 #define REG_USART3_RTOR (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
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57 #define REG_USART3_TTGR (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
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58 #define REG_USART3_FIDI (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
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59 #define REG_USART3_NER (0x400A4044U) /**< \brief (USART3) Number of Errors Register */
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60 #define REG_USART3_IF (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
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61 #define REG_USART3_MAN (0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
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62 #define REG_USART3_LINMR (0x400A4054U) /**< \brief (USART3) LIN Mode Register */
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63 #define REG_USART3_LINIR (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
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64 #define REG_USART3_WPMR (0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
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65 #define REG_USART3_WPSR (0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
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66 #define REG_USART3_RPR (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
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67 #define REG_USART3_RCR (0x400A4104U) /**< \brief (USART3) Receive Counter Register */
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68 #define REG_USART3_TPR (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
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69 #define REG_USART3_TCR (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
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70 #define REG_USART3_RNPR (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
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71 #define REG_USART3_RNCR (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
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72 #define REG_USART3_TNPR (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
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73 #define REG_USART3_TNCR (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
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74 #define REG_USART3_PTCR (0x400A4120U) /**< \brief (USART3) Transfer Control Register */
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75 #define REG_USART3_PTSR (0x400A4124U) /**< \brief (USART3) Transfer Status Register */
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77 #define REG_USART3_CR (*(WoReg*)0x400A4000U) /**< \brief (USART3) Control Register */
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78 #define REG_USART3_MR (*(RwReg*)0x400A4004U) /**< \brief (USART3) Mode Register */
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79 #define REG_USART3_IER (*(WoReg*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
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80 #define REG_USART3_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
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81 #define REG_USART3_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
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82 #define REG_USART3_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART3) Channel Status Register */
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83 #define REG_USART3_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
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84 #define REG_USART3_THR (*(WoReg*)0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
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85 #define REG_USART3_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
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86 #define REG_USART3_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
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87 #define REG_USART3_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
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88 #define REG_USART3_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
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89 #define REG_USART3_NER (*(RoReg*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */
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90 #define REG_USART3_IF (*(RwReg*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
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91 #define REG_USART3_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
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92 #define REG_USART3_LINMR (*(RwReg*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */
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93 #define REG_USART3_LINIR (*(RwReg*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
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94 #define REG_USART3_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
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95 #define REG_USART3_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
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96 #define REG_USART3_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
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97 #define REG_USART3_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */
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98 #define REG_USART3_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
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99 #define REG_USART3_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
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100 #define REG_USART3_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
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101 #define REG_USART3_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
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102 #define REG_USART3_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
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103 #define REG_USART3_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
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104 #define REG_USART3_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */
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105 #define REG_USART3_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */
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106 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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108 #endif /* _SAM3XA_USART3_INSTANCE_ */
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