1 /**************************************************************************//**
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2 * @file efm32pg1b_adc.h
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3 * @brief EFM32PG1B_ADC register and bit field definitions
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5 ******************************************************************************
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7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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35 ******************************************************************************/
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36 /**************************************************************************//**
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37 * @defgroup EFM32PG1B_ADC
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39 * @brief EFM32PG1B_ADC Register Declaration
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40 *****************************************************************************/
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43 __IO uint32_t CTRL; /**< Control Register */
\r
44 uint32_t RESERVED0[1]; /**< Reserved for future use **/
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45 __IO uint32_t CMD; /**< Command Register */
\r
46 __I uint32_t STATUS; /**< Status Register */
\r
47 __IO uint32_t SINGLECTRL; /**< Single Channel Control Register */
\r
48 __IO uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */
\r
49 __IO uint32_t SCANCTRL; /**< Scan Control Register */
\r
50 __IO uint32_t SCANCTRLX; /**< Scan Control Register continued */
\r
51 __IO uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */
\r
52 __IO uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */
\r
53 __IO uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */
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54 __IO uint32_t CMPTHR; /**< Compare Threshold Register */
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55 __IO uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation */
\r
56 __IO uint32_t CAL; /**< Calibration Register */
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57 __I uint32_t IF; /**< Interrupt Flag Register */
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58 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
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59 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
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60 __IO uint32_t IEN; /**< Interrupt Enable Register */
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61 __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
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62 __I uint32_t SCANDATA; /**< Scan Conversion Result Data */
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63 __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
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64 __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
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65 uint32_t RESERVED1[4]; /**< Reserved for future use **/
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66 __I uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */
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67 __I uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */
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69 uint32_t RESERVED2[3]; /**< Reserved for future use **/
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70 __I uint32_t APORTREQ; /**< APORT Request Status Register */
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71 __I uint32_t APORTCONFLICT; /**< APORT BUS Request Status Register */
\r
72 __I uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */
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73 __I uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */
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74 __IO uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */
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75 __IO uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */
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76 __IO uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */
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77 } ADC_TypeDef; /** @} */
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79 /**************************************************************************//**
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80 * @defgroup EFM32PG1B_ADC_BitFields
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82 *****************************************************************************/
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84 /* Bit fields for ADC CTRL */
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85 #define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
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86 #define _ADC_CTRL_MASK 0x2F7F7FDFUL /**< Mask for ADC_CTRL */
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87 #define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
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88 #define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
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89 #define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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90 #define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
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91 #define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */
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92 #define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */
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93 #define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
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94 #define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
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95 #define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
\r
96 #define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */
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97 #define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */
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98 #define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
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99 #define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */
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100 #define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */
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101 #define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */
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102 #define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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103 #define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */
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104 #define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */
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105 #define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */
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106 #define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */
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107 #define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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108 #define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
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109 #define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */
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110 #define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */
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111 #define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */
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112 #define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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113 #define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
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114 #define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */
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115 #define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */
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116 #define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */
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117 #define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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118 #define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */
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119 #define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */
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120 #define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */
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121 #define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */
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122 #define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */
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123 #define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */
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124 #define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */
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125 #define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */
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126 #define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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127 #define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */
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128 #define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */
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129 #define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */
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130 #define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */
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131 #define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */
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132 #define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
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133 #define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
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134 #define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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135 #define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
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136 #define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
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137 #define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
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138 #define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
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139 #define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */
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140 #define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
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141 #define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
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142 #define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
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143 #define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
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144 #define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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145 #define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
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146 #define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
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147 #define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
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148 #define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
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149 #define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
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150 #define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
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151 #define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
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152 #define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
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153 #define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
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154 #define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
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155 #define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
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156 #define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
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157 #define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
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158 #define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
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159 #define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
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160 #define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
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161 #define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
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162 #define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
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163 #define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
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164 #define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
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165 #define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
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166 #define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
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167 #define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
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168 #define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
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169 #define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
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170 #define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */
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171 #define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */
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172 #define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */
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173 #define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
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174 #define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */
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175 #define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */
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176 #define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */
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177 #define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */
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178 #define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */
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180 /* Bit fields for ADC CMD */
\r
181 #define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
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182 #define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
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183 #define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */
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184 #define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
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185 #define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
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186 #define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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187 #define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
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188 #define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */
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189 #define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
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190 #define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
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191 #define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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192 #define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
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193 #define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
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194 #define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
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195 #define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
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196 #define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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197 #define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
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198 #define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
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199 #define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
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200 #define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
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201 #define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
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202 #define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
\r
204 /* Bit fields for ADC STATUS */
\r
205 #define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
\r
206 #define _ADC_STATUS_MASK 0x00031F03UL /**< Mask for ADC_STATUS */
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207 #define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */
\r
208 #define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
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209 #define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
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210 #define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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211 #define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
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212 #define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
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213 #define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
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214 #define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
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215 #define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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216 #define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
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217 #define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */
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218 #define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
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219 #define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
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220 #define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
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221 #define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
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222 #define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
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223 #define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
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224 #define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
\r
225 #define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
226 #define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
227 #define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */
\r
228 #define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */
\r
229 #define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
230 #define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */
\r
231 #define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */
\r
232 #define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
233 #define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */
\r
234 #define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */
\r
235 #define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
\r
236 #define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
\r
237 #define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
\r
238 #define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
239 #define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
240 #define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */
\r
241 #define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
\r
242 #define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
\r
243 #define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
244 #define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
245 #define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
\r
246 #define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
\r
247 #define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
\r
248 #define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
\r
249 #define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
\r
251 /* Bit fields for ADC SINGLECTRL */
\r
252 #define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */
\r
253 #define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */
\r
254 #define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */
\r
255 #define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
\r
256 #define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
\r
257 #define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
258 #define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
259 #define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */
\r
260 #define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
\r
261 #define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
\r
262 #define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
263 #define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
264 #define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */
\r
265 #define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
\r
266 #define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
\r
267 #define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
268 #define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
\r
269 #define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
\r
270 #define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
271 #define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
\r
272 #define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
\r
273 #define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */
\r
274 #define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */
\r
275 #define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
276 #define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
\r
277 #define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
\r
278 #define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
\r
279 #define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
\r
280 #define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
281 #define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
\r
282 #define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
\r
283 #define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
\r
284 #define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */
\r
285 #define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */
\r
286 #define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */
\r
287 #define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
288 #define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
\r
289 #define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
\r
290 #define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
\r
291 #define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */
\r
292 #define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
\r
293 #define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
\r
294 #define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
\r
295 #define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */
\r
296 #define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
297 #define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
\r
298 #define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
\r
299 #define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */
\r
300 #define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 5) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
\r
301 #define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
\r
302 #define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
\r
303 #define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
\r
304 #define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */
\r
305 #define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */
\r
306 #define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */
\r
307 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
\r
308 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
\r
309 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
\r
310 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
\r
311 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
\r
312 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
\r
313 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
\r
314 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
\r
315 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
\r
316 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
\r
317 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
\r
318 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
\r
319 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
\r
320 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
\r
321 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
\r
322 #define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
\r
323 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
\r
324 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
\r
325 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
\r
326 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
\r
327 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
\r
328 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
\r
329 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
\r
330 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
\r
331 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
\r
332 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
\r
333 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
\r
334 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
\r
335 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
\r
336 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
\r
337 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
\r
338 #define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
\r
339 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
\r
340 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
\r
341 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
\r
342 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
\r
343 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
\r
344 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
\r
345 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
\r
346 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
\r
347 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
\r
348 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
\r
349 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
\r
350 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
\r
351 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
\r
352 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
\r
353 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
\r
354 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
\r
355 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
\r
356 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
\r
357 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
\r
358 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
\r
359 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
\r
360 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
\r
361 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
\r
362 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
\r
363 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
\r
364 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
\r
365 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
\r
366 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
\r
367 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
\r
368 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
\r
369 #define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
\r
370 #define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
\r
371 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
\r
372 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
\r
373 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
\r
374 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
\r
375 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
\r
376 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
\r
377 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
\r
378 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
\r
379 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
\r
380 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
\r
381 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
\r
382 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
\r
383 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
\r
384 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
\r
385 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
\r
386 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
\r
387 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
\r
388 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
\r
389 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
\r
390 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
\r
391 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
\r
392 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
\r
393 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
\r
394 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
\r
395 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
\r
396 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
\r
397 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
\r
398 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
\r
399 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
\r
400 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
\r
401 #define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
\r
402 #define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
\r
403 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
\r
404 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
\r
405 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
\r
406 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
\r
407 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
\r
408 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
\r
409 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
\r
410 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
\r
411 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
\r
412 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
\r
413 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
\r
414 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
\r
415 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
\r
416 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
\r
417 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
\r
418 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
\r
419 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
\r
420 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
\r
421 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
\r
422 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
\r
423 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
\r
424 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
\r
425 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
\r
426 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
\r
427 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
\r
428 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
\r
429 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
\r
430 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
\r
431 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
\r
432 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
\r
433 #define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
\r
434 #define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
\r
435 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
\r
436 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
\r
437 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
\r
438 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
\r
439 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
\r
440 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
\r
441 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
\r
442 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
\r
443 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
\r
444 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
\r
445 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
\r
446 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
\r
447 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
\r
448 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
\r
449 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
\r
450 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
\r
451 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
\r
452 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
\r
453 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
\r
454 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
\r
455 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
\r
456 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
\r
457 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
\r
458 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
\r
459 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
\r
460 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
\r
461 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
\r
462 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
\r
463 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
\r
464 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
\r
465 #define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
\r
466 #define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
\r
467 #define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */
\r
468 #define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */
\r
469 #define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */
\r
470 #define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */
\r
471 #define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */
\r
472 #define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */
\r
473 #define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */
\r
474 #define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */
\r
475 #define _ADC_SINGLECTRL_POSSEL_SP0 0x000000F2UL /**< Mode SP0 for ADC_SINGLECTRL */
\r
476 #define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */
\r
477 #define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
\r
478 #define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */
\r
479 #define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */
\r
480 #define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */
\r
481 #define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
\r
482 #define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */
\r
483 #define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
484 #define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */
\r
485 #define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
\r
486 #define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
\r
487 #define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
\r
488 #define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
\r
489 #define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
\r
490 #define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
\r
491 #define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
\r
492 #define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
\r
493 #define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
\r
494 #define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
\r
495 #define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
\r
496 #define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
\r
497 #define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
\r
498 #define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
\r
499 #define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
\r
500 #define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
\r
501 #define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
\r
502 #define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
\r
503 #define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
\r
504 #define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
\r
505 #define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
\r
506 #define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
\r
507 #define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
\r
508 #define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
\r
509 #define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
\r
510 #define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
\r
511 #define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
\r
512 #define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
\r
513 #define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
\r
514 #define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
\r
515 #define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
\r
516 #define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
\r
517 #define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
\r
518 #define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
\r
519 #define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
\r
520 #define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
\r
521 #define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
\r
522 #define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
\r
523 #define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
\r
524 #define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
\r
525 #define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
\r
526 #define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
\r
527 #define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
\r
528 #define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
\r
529 #define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
\r
530 #define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
\r
531 #define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
\r
532 #define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
\r
533 #define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
\r
534 #define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
\r
535 #define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
\r
536 #define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
\r
537 #define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
\r
538 #define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
\r
539 #define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
\r
540 #define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
\r
541 #define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
\r
542 #define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
\r
543 #define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
\r
544 #define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
\r
545 #define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
\r
546 #define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
\r
547 #define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
\r
548 #define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
\r
549 #define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
\r
550 #define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
\r
551 #define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
\r
552 #define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
\r
553 #define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
\r
554 #define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
\r
555 #define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
\r
556 #define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
\r
557 #define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
\r
558 #define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
\r
559 #define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
\r
560 #define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
\r
561 #define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
\r
562 #define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
\r
563 #define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
\r
564 #define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
\r
565 #define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
\r
566 #define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
\r
567 #define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
\r
568 #define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
\r
569 #define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
\r
570 #define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
\r
571 #define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
\r
572 #define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
\r
573 #define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
\r
574 #define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
\r
575 #define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
\r
576 #define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
\r
577 #define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
\r
578 #define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
\r
579 #define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
\r
580 #define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
\r
581 #define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
\r
582 #define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
\r
583 #define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
\r
584 #define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
\r
585 #define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
\r
586 #define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
\r
587 #define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
\r
588 #define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
\r
589 #define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
\r
590 #define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
\r
591 #define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
\r
592 #define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
\r
593 #define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
\r
594 #define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
\r
595 #define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
\r
596 #define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
\r
597 #define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
\r
598 #define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
\r
599 #define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
\r
600 #define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
\r
601 #define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
\r
602 #define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
\r
603 #define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
\r
604 #define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
\r
605 #define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
\r
606 #define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
\r
607 #define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
\r
608 #define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
\r
609 #define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
\r
610 #define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
\r
611 #define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
\r
612 #define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
\r
613 #define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
\r
614 #define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
\r
615 #define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
\r
616 #define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
\r
617 #define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
\r
618 #define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
\r
619 #define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
\r
620 #define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
\r
621 #define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
\r
622 #define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
\r
623 #define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
\r
624 #define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
\r
625 #define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
\r
626 #define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
\r
627 #define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
\r
628 #define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
\r
629 #define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
\r
630 #define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
\r
631 #define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
\r
632 #define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
\r
633 #define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
\r
634 #define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
\r
635 #define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
\r
636 #define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
\r
637 #define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
\r
638 #define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
\r
639 #define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
\r
640 #define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
\r
641 #define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
\r
642 #define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
\r
643 #define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
\r
644 #define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
\r
645 #define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */
\r
646 #define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */
\r
647 #define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */
\r
648 #define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */
\r
649 #define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */
\r
650 #define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */
\r
651 #define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */
\r
652 #define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */
\r
653 #define ADC_SINGLECTRL_POSSEL_SP0 (_ADC_SINGLECTRL_POSSEL_SP0 << 8) /**< Shifted mode SP0 for ADC_SINGLECTRL */
\r
654 #define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
\r
655 #define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
\r
656 #define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */
\r
657 #define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */
\r
658 #define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */
\r
659 #define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
\r
660 #define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */
\r
661 #define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
662 #define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
\r
663 #define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */
\r
664 #define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */
\r
665 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */
\r
666 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */
\r
667 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */
\r
668 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */
\r
669 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */
\r
670 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */
\r
671 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */
\r
672 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */
\r
673 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */
\r
674 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */
\r
675 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */
\r
676 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */
\r
677 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */
\r
678 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */
\r
679 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */
\r
680 #define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */
\r
681 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */
\r
682 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */
\r
683 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */
\r
684 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */
\r
685 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */
\r
686 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */
\r
687 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */
\r
688 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */
\r
689 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */
\r
690 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */
\r
691 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */
\r
692 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */
\r
693 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */
\r
694 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */
\r
695 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */
\r
696 #define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */
\r
697 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */
\r
698 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */
\r
699 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */
\r
700 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */
\r
701 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */
\r
702 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */
\r
703 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */
\r
704 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */
\r
705 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */
\r
706 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */
\r
707 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */
\r
708 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */
\r
709 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */
\r
710 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */
\r
711 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */
\r
712 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */
\r
713 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */
\r
714 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */
\r
715 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */
\r
716 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */
\r
717 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */
\r
718 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */
\r
719 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */
\r
720 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */
\r
721 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */
\r
722 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */
\r
723 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */
\r
724 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */
\r
725 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */
\r
726 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */
\r
727 #define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */
\r
728 #define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */
\r
729 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */
\r
730 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */
\r
731 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */
\r
732 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */
\r
733 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */
\r
734 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */
\r
735 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */
\r
736 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */
\r
737 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */
\r
738 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */
\r
739 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */
\r
740 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */
\r
741 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */
\r
742 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */
\r
743 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */
\r
744 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */
\r
745 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */
\r
746 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */
\r
747 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */
\r
748 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */
\r
749 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */
\r
750 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */
\r
751 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */
\r
752 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */
\r
753 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */
\r
754 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */
\r
755 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */
\r
756 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */
\r
757 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */
\r
758 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */
\r
759 #define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */
\r
760 #define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */
\r
761 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */
\r
762 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */
\r
763 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */
\r
764 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */
\r
765 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */
\r
766 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */
\r
767 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */
\r
768 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */
\r
769 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */
\r
770 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */
\r
771 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */
\r
772 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */
\r
773 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */
\r
774 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */
\r
775 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */
\r
776 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */
\r
777 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */
\r
778 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */
\r
779 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */
\r
780 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */
\r
781 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */
\r
782 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */
\r
783 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */
\r
784 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */
\r
785 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */
\r
786 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */
\r
787 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */
\r
788 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */
\r
789 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */
\r
790 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */
\r
791 #define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */
\r
792 #define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */
\r
793 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */
\r
794 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */
\r
795 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */
\r
796 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */
\r
797 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */
\r
798 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */
\r
799 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */
\r
800 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */
\r
801 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */
\r
802 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */
\r
803 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */
\r
804 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */
\r
805 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */
\r
806 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */
\r
807 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */
\r
808 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */
\r
809 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */
\r
810 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */
\r
811 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */
\r
812 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */
\r
813 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */
\r
814 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */
\r
815 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */
\r
816 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */
\r
817 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */
\r
818 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */
\r
819 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */
\r
820 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */
\r
821 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */
\r
822 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */
\r
823 #define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */
\r
824 #define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */
\r
825 #define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */
\r
826 #define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
827 #define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */
\r
828 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */
\r
829 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */
\r
830 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */
\r
831 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */
\r
832 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */
\r
833 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */
\r
834 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */
\r
835 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */
\r
836 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */
\r
837 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */
\r
838 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */
\r
839 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */
\r
840 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */
\r
841 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */
\r
842 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */
\r
843 #define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */
\r
844 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */
\r
845 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */
\r
846 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */
\r
847 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */
\r
848 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */
\r
849 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */
\r
850 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */
\r
851 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */
\r
852 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */
\r
853 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */
\r
854 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */
\r
855 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */
\r
856 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */
\r
857 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */
\r
858 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */
\r
859 #define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */
\r
860 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */
\r
861 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */
\r
862 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */
\r
863 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */
\r
864 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */
\r
865 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */
\r
866 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */
\r
867 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */
\r
868 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */
\r
869 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */
\r
870 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */
\r
871 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */
\r
872 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */
\r
873 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */
\r
874 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */
\r
875 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */
\r
876 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */
\r
877 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */
\r
878 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */
\r
879 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */
\r
880 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */
\r
881 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */
\r
882 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */
\r
883 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */
\r
884 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */
\r
885 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */
\r
886 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */
\r
887 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */
\r
888 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */
\r
889 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */
\r
890 #define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */
\r
891 #define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */
\r
892 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */
\r
893 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */
\r
894 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */
\r
895 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */
\r
896 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */
\r
897 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */
\r
898 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */
\r
899 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */
\r
900 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */
\r
901 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */
\r
902 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */
\r
903 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */
\r
904 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */
\r
905 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */
\r
906 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */
\r
907 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */
\r
908 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */
\r
909 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */
\r
910 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */
\r
911 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */
\r
912 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */
\r
913 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */
\r
914 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */
\r
915 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */
\r
916 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */
\r
917 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */
\r
918 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */
\r
919 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */
\r
920 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */
\r
921 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */
\r
922 #define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */
\r
923 #define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */
\r
924 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */
\r
925 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */
\r
926 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */
\r
927 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */
\r
928 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */
\r
929 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */
\r
930 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */
\r
931 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */
\r
932 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */
\r
933 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */
\r
934 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */
\r
935 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */
\r
936 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */
\r
937 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */
\r
938 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */
\r
939 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */
\r
940 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */
\r
941 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */
\r
942 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */
\r
943 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */
\r
944 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */
\r
945 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */
\r
946 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */
\r
947 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */
\r
948 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */
\r
949 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */
\r
950 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */
\r
951 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */
\r
952 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */
\r
953 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */
\r
954 #define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */
\r
955 #define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */
\r
956 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */
\r
957 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */
\r
958 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */
\r
959 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */
\r
960 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */
\r
961 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */
\r
962 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */
\r
963 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */
\r
964 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */
\r
965 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */
\r
966 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */
\r
967 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */
\r
968 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */
\r
969 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */
\r
970 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */
\r
971 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */
\r
972 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */
\r
973 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */
\r
974 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */
\r
975 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */
\r
976 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */
\r
977 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */
\r
978 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */
\r
979 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */
\r
980 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */
\r
981 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */
\r
982 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */
\r
983 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */
\r
984 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */
\r
985 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */
\r
986 #define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */
\r
987 #define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */
\r
988 #define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */
\r
989 #define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
990 #define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */
\r
991 #define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */
\r
992 #define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */
\r
993 #define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
994 #define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
\r
995 #define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
\r
996 #define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */
\r
997 #define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
\r
998 #define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
\r
999 #define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
\r
1000 #define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
\r
1001 #define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
\r
1002 #define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
\r
1003 #define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
\r
1004 #define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
1005 #define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
\r
1006 #define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
\r
1007 #define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */
\r
1008 #define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
\r
1009 #define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
\r
1010 #define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
\r
1011 #define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
\r
1012 #define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
\r
1013 #define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
\r
1014 #define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
\r
1015 #define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */
\r
1016 #define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */
\r
1017 #define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */
\r
1018 #define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
1019 #define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
1020 #define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */
\r
1021 #define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */
\r
1022 #define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */
\r
1023 #define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
\r
1024 #define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
\r
1026 /* Bit fields for ADC SINGLECTRLX */
\r
1027 #define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */
\r
1028 #define _ADC_SINGLECTRLX_MASK 0x0F1F7FFFUL /**< Mask for ADC_SINGLECTRLX */
\r
1029 #define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */
\r
1030 #define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */
\r
1031 #define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1032 #define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */
\r
1033 #define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */
\r
1034 #define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */
\r
1035 #define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */
\r
1036 #define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */
\r
1037 #define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */
\r
1038 #define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */
\r
1039 #define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */
\r
1040 #define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1041 #define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */
\r
1042 #define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */
\r
1043 #define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */
\r
1044 #define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */
\r
1045 #define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */
\r
1046 #define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */
\r
1047 #define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */
\r
1048 #define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */
\r
1049 #define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable 1/3 scaling on VREF */
\r
1050 #define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
\r
1051 #define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
\r
1052 #define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1053 #define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1054 #define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */
\r
1055 #define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */
\r
1056 #define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1057 #define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1058 #define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */
\r
1059 #define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */
\r
1060 #define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1061 #define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1062 #define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */
\r
1063 #define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */
\r
1064 #define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1065 #define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1066 #define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */
\r
1067 #define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */
\r
1068 #define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */
\r
1069 #define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1070 #define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */
\r
1071 #define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */
\r
1072 #define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1073 #define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */
\r
1074 #define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */
\r
1075 #define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */
\r
1076 #define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */
\r
1077 #define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */
\r
1078 #define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1079 #define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */
\r
1080 #define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */
\r
1081 #define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1082 #define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */
\r
1083 #define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */
\r
1084 #define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */
\r
1085 #define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */
\r
1086 #define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1087 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */
\r
1088 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */
\r
1089 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */
\r
1090 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */
\r
1091 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */
\r
1092 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */
\r
1093 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */
\r
1094 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */
\r
1095 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */
\r
1096 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */
\r
1097 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */
\r
1098 #define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */
\r
1099 #define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1100 #define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */
\r
1101 #define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */
\r
1102 #define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */
\r
1103 #define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */
\r
1104 #define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */
\r
1105 #define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */
\r
1106 #define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */
\r
1107 #define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */
\r
1108 #define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */
\r
1109 #define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */
\r
1110 #define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */
\r
1111 #define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */
\r
1112 #define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 24 /**< Shift value for ADC_CONVSTARTDELAY */
\r
1113 #define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */
\r
1114 #define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1115 #define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1116 #define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */
\r
1117 #define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
\r
1118 #define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
\r
1119 #define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */
\r
1120 #define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */
\r
1122 /* Bit fields for ADC SCANCTRL */
\r
1123 #define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
\r
1124 #define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */
\r
1125 #define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
\r
1126 #define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
\r
1127 #define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
\r
1128 #define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1129 #define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1130 #define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
\r
1131 #define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
\r
1132 #define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
\r
1133 #define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1134 #define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1135 #define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
\r
1136 #define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
\r
1137 #define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
\r
1138 #define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1139 #define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
\r
1140 #define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
\r
1141 #define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1142 #define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
\r
1143 #define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
\r
1144 #define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */
\r
1145 #define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */
\r
1146 #define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1147 #define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
\r
1148 #define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
\r
1149 #define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
\r
1150 #define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
\r
1151 #define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1152 #define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */
\r
1153 #define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */
\r
1154 #define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */
\r
1155 #define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */
\r
1156 #define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */
\r
1157 #define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */
\r
1158 #define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1159 #define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
\r
1160 #define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
\r
1161 #define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
\r
1162 #define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */
\r
1163 #define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
\r
1164 #define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
\r
1165 #define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
\r
1166 #define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */
\r
1167 #define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1168 #define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */
\r
1169 #define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */
\r
1170 #define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */
\r
1171 #define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 5) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
\r
1172 #define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
\r
1173 #define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
\r
1174 #define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
\r
1175 #define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */
\r
1176 #define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */
\r
1177 #define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */
\r
1178 #define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1179 #define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
\r
1180 #define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
\r
1181 #define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */
\r
1182 #define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */
\r
1183 #define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */
\r
1184 #define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */
\r
1185 #define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */
\r
1186 #define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */
\r
1187 #define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */
\r
1188 #define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */
\r
1189 #define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1190 #define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
\r
1191 #define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
\r
1192 #define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */
\r
1193 #define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
\r
1194 #define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
\r
1195 #define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
\r
1196 #define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
\r
1197 #define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
\r
1198 #define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
\r
1199 #define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
\r
1200 #define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */
\r
1201 #define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */
\r
1202 #define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */
\r
1203 #define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1204 #define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1205 #define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */
\r
1206 #define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */
\r
1207 #define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */
\r
1208 #define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
\r
1209 #define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
\r
1211 /* Bit fields for ADC SCANCTRLX */
\r
1212 #define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */
\r
1213 #define _ADC_SCANCTRLX_MASK 0x0F1F7FFFUL /**< Mask for ADC_SCANCTRLX */
\r
1214 #define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */
\r
1215 #define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */
\r
1216 #define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1217 #define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */
\r
1218 #define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */
\r
1219 #define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */
\r
1220 #define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */
\r
1221 #define _ADC_SCANCTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SCANCTRLX */
\r
1222 #define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */
\r
1223 #define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */
\r
1224 #define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */
\r
1225 #define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1226 #define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */
\r
1227 #define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */
\r
1228 #define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */
\r
1229 #define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */
\r
1230 #define ADC_SCANCTRLX_VREFSEL_VENTROPY (_ADC_SCANCTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SCANCTRLX */
\r
1231 #define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */
\r
1232 #define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */
\r
1233 #define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */
\r
1234 #define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed 1/3 scaling on VREF */
\r
1235 #define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */
\r
1236 #define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */
\r
1237 #define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1238 #define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1239 #define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */
\r
1240 #define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */
\r
1241 #define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1242 #define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1243 #define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */
\r
1244 #define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */
\r
1245 #define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1246 #define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1247 #define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */
\r
1248 #define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */
\r
1249 #define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1250 #define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1251 #define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */
\r
1252 #define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */
\r
1253 #define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */
\r
1254 #define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1255 #define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */
\r
1256 #define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */
\r
1257 #define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1258 #define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */
\r
1259 #define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */
\r
1260 #define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */
\r
1261 #define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */
\r
1262 #define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */
\r
1263 #define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1264 #define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */
\r
1265 #define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */
\r
1266 #define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1267 #define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */
\r
1268 #define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */
\r
1269 #define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */
\r
1270 #define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */
\r
1271 #define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1272 #define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */
\r
1273 #define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */
\r
1274 #define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */
\r
1275 #define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */
\r
1276 #define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */
\r
1277 #define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */
\r
1278 #define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */
\r
1279 #define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */
\r
1280 #define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */
\r
1281 #define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */
\r
1282 #define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */
\r
1283 #define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */
\r
1284 #define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1285 #define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */
\r
1286 #define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */
\r
1287 #define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */
\r
1288 #define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */
\r
1289 #define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */
\r
1290 #define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */
\r
1291 #define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */
\r
1292 #define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */
\r
1293 #define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */
\r
1294 #define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */
\r
1295 #define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */
\r
1296 #define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */
\r
1297 #define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 24 /**< Shift value for ADC_CONVSTARTDELAY */
\r
1298 #define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7000000UL /**< Bit mask for ADC_CONVSTARTDELAY */
\r
1299 #define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1300 #define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1301 #define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */
\r
1302 #define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */
\r
1303 #define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */
\r
1304 #define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */
\r
1305 #define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */
\r
1307 /* Bit fields for ADC SCANMASK */
\r
1308 #define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */
\r
1309 #define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */
\r
1310 #define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */
\r
1311 #define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */
\r
1312 #define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */
\r
1313 #define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
\r
1314 #define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */
\r
1315 #define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */
\r
1316 #define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */
\r
1317 #define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */
\r
1318 #define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
\r
1319 #define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */
\r
1320 #define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */
\r
1321 #define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */
\r
1322 #define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
\r
1323 #define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */
\r
1324 #define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */
\r
1325 #define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
\r
1326 #define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */
\r
1327 #define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */
\r
1328 #define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */
\r
1329 #define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */
\r
1330 #define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */
\r
1331 #define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */
\r
1332 #define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
\r
1333 #define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */
\r
1334 #define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */
\r
1335 #define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
\r
1336 #define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */
\r
1337 #define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */
\r
1338 #define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */
\r
1339 #define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
\r
1340 #define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */
\r
1341 #define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */
\r
1342 #define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */
\r
1343 #define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
\r
1344 #define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */
\r
1345 #define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */
\r
1346 #define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */
\r
1347 #define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */
\r
1348 #define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */
\r
1349 #define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */
\r
1350 #define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */
\r
1351 #define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */
\r
1352 #define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */
\r
1353 #define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */
\r
1354 #define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */
\r
1355 #define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */
\r
1356 #define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */
\r
1357 #define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */
\r
1358 #define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */
\r
1359 #define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */
\r
1360 #define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */
\r
1361 #define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */
\r
1362 #define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */
\r
1363 #define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */
\r
1364 #define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */
\r
1365 #define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */
\r
1366 #define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */
\r
1367 #define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */
\r
1368 #define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */
\r
1369 #define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */
\r
1370 #define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */
\r
1371 #define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */
\r
1372 #define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */
\r
1373 #define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */
\r
1374 #define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */
\r
1375 #define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */
\r
1376 #define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */
\r
1377 #define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */
\r
1378 #define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */
\r
1379 #define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */
\r
1380 #define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */
\r
1381 #define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */
\r
1382 #define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */
\r
1383 #define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */
\r
1384 #define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */
\r
1385 #define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */
\r
1386 #define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */
\r
1387 #define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */
\r
1388 #define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */
\r
1389 #define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */
\r
1390 #define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */
\r
1391 #define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */
\r
1392 #define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */
\r
1393 #define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */
\r
1394 #define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */
\r
1395 #define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */
\r
1396 #define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */
\r
1397 #define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */
\r
1398 #define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */
\r
1399 #define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */
\r
1400 #define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */
\r
1401 #define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */
\r
1402 #define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */
\r
1403 #define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */
\r
1404 #define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */
\r
1405 #define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */
\r
1406 #define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */
\r
1407 #define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */
\r
1408 #define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */
\r
1409 #define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */
\r
1410 #define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */
\r
1411 #define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */
\r
1412 #define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */
\r
1413 #define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */
\r
1414 #define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */
\r
1415 #define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */
\r
1416 #define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */
\r
1417 #define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */
\r
1418 #define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */
\r
1419 #define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */
\r
1420 #define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */
\r
1421 #define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */
\r
1422 #define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */
\r
1423 #define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */
\r
1424 #define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */
\r
1425 #define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */
\r
1426 #define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */
\r
1427 #define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */
\r
1428 #define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */
\r
1429 #define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */
\r
1430 #define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */
\r
1431 #define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */
\r
1432 #define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */
\r
1433 #define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */
\r
1434 #define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */
\r
1435 #define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */
\r
1436 #define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */
\r
1437 #define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */
\r
1438 #define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */
\r
1439 #define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */
\r
1440 #define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */
\r
1441 #define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */
\r
1443 /* Bit fields for ADC SCANINPUTSEL */
\r
1444 #define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */
\r
1445 #define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */
\r
1446 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */
\r
1447 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */
\r
1448 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
\r
1449 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1450 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1451 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1452 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1453 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1454 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1455 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1456 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1457 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1458 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1459 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1460 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1461 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1462 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1463 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1464 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1465 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1466 #define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1467 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
\r
1468 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1469 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1470 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1471 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1472 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1473 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1474 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1475 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1476 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1477 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1478 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1479 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1480 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1481 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1482 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1483 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1484 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1485 #define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1486 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */
\r
1487 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */
\r
1488 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
\r
1489 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1490 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1491 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1492 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1493 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1494 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1495 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1496 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1497 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1498 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1499 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1500 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1501 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1502 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1503 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1504 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1505 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1506 #define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1507 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
\r
1508 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1509 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1510 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1511 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1512 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1513 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1514 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1515 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1516 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1517 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1518 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1519 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1520 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1521 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1522 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1523 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1524 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1525 #define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1526 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */
\r
1527 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */
\r
1528 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
\r
1529 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1530 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1531 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1532 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1533 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1534 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1535 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1536 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1537 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1538 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1539 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1540 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1541 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1542 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1543 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1544 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1545 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1546 #define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1547 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
\r
1548 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1549 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1550 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1551 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1552 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1553 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1554 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1555 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1556 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1557 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1558 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1559 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1560 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1561 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1562 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1563 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1564 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1565 #define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1566 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */
\r
1567 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */
\r
1568 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */
\r
1569 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1570 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1571 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1572 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1573 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1574 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1575 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1576 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1577 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1578 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1579 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1580 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1581 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1582 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1583 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1584 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1585 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1586 #define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1587 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */
\r
1588 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */
\r
1589 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */
\r
1590 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */
\r
1591 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */
\r
1592 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */
\r
1593 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */
\r
1594 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */
\r
1595 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */
\r
1596 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */
\r
1597 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */
\r
1598 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */
\r
1599 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */
\r
1600 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */
\r
1601 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */
\r
1602 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */
\r
1603 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */
\r
1604 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */
\r
1605 #define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */
\r
1607 /* Bit fields for ADC SCANNEGSEL */
\r
1608 #define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */
\r
1609 #define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */
\r
1610 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */
\r
1611 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */
\r
1612 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1613 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
\r
1614 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
\r
1615 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
\r
1616 #define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
\r
1617 #define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1618 #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
\r
1619 #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
\r
1620 #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
\r
1621 #define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
\r
1622 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */
\r
1623 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */
\r
1624 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
\r
1625 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1626 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
\r
1627 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
\r
1628 #define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
\r
1629 #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
\r
1630 #define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1631 #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
\r
1632 #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
\r
1633 #define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
\r
1634 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */
\r
1635 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */
\r
1636 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
\r
1637 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
\r
1638 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1639 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
\r
1640 #define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
\r
1641 #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
\r
1642 #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
\r
1643 #define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1644 #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
\r
1645 #define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
\r
1646 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */
\r
1647 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */
\r
1648 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */
\r
1649 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */
\r
1650 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */
\r
1651 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1652 #define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */
\r
1653 #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */
\r
1654 #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */
\r
1655 #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */
\r
1656 #define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1657 #define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */
\r
1658 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */
\r
1659 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */
\r
1660 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
\r
1661 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1662 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
\r
1663 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
\r
1664 #define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
\r
1665 #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
\r
1666 #define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1667 #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
\r
1668 #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
\r
1669 #define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
\r
1670 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */
\r
1671 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */
\r
1672 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
\r
1673 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
\r
1674 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1675 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
\r
1676 #define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
\r
1677 #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
\r
1678 #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
\r
1679 #define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1680 #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
\r
1681 #define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
\r
1682 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */
\r
1683 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */
\r
1684 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
\r
1685 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
\r
1686 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
\r
1687 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1688 #define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
\r
1689 #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
\r
1690 #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
\r
1691 #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
\r
1692 #define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1693 #define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
\r
1694 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */
\r
1695 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */
\r
1696 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */
\r
1697 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */
\r
1698 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */
\r
1699 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */
\r
1700 #define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */
\r
1701 #define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */
\r
1702 #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */
\r
1703 #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */
\r
1704 #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */
\r
1705 #define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */
\r
1707 /* Bit fields for ADC CMPTHR */
\r
1708 #define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */
\r
1709 #define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */
\r
1710 #define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */
\r
1711 #define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */
\r
1712 #define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */
\r
1713 #define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */
\r
1714 #define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */
\r
1715 #define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */
\r
1716 #define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */
\r
1717 #define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */
\r
1719 /* Bit fields for ADC BIASPROG */
\r
1720 #define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */
\r
1721 #define _ADC_BIASPROG_MASK 0x0000100FUL /**< Mask for ADC_BIASPROG */
\r
1722 #define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */
\r
1723 #define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */
\r
1724 #define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
\r
1725 #define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */
\r
1726 #define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */
\r
1727 #define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */
\r
1728 #define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */
\r
1729 #define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */
\r
1730 #define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */
\r
1731 #define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
\r
1732 #define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */
\r
1733 #define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */
\r
1734 #define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */
\r
1735 #define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */
\r
1736 #define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */
\r
1737 #define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */
\r
1738 #define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Set Vfault_clr flag */
\r
1739 #define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */
\r
1740 #define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */
\r
1741 #define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */
\r
1742 #define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */
\r
1744 /* Bit fields for ADC CAL */
\r
1745 #define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */
\r
1746 #define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */
\r
1747 #define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
\r
1748 #define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */
\r
1749 #define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */
\r
1750 #define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1751 #define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */
\r
1752 #define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */
\r
1753 #define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */
\r
1754 #define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1755 #define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
\r
1756 #define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
\r
1757 #define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
\r
1758 #define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1759 #define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */
\r
1760 #define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */
\r
1761 #define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */
\r
1762 #define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
\r
1763 #define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1764 #define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
\r
1765 #define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */
\r
1766 #define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */
\r
1767 #define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1768 #define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */
\r
1769 #define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */
\r
1770 #define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */
\r
1771 #define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1772 #define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
\r
1773 #define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
\r
1774 #define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */
\r
1775 #define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1776 #define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */
\r
1777 #define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */
\r
1778 #define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */
\r
1779 #define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
\r
1780 #define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */
\r
1782 /* Bit fields for ADC IF */
\r
1783 #define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
\r
1784 #define _ADC_IF_MASK 0x03030F03UL /**< Mask for ADC_IF */
\r
1785 #define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
\r
1786 #define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
\r
1787 #define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
\r
1788 #define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1789 #define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
\r
1790 #define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
\r
1791 #define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
\r
1792 #define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
\r
1793 #define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1794 #define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
\r
1795 #define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */
\r
1796 #define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
1797 #define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
1798 #define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1799 #define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
\r
1800 #define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */
\r
1801 #define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
1802 #define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
1803 #define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1804 #define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
\r
1805 #define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single Result Underflow Interrupt Flag */
\r
1806 #define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
\r
1807 #define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
\r
1808 #define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1809 #define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */
\r
1810 #define ADC_IF_SCANUF (0x1UL << 11) /**< Scan Result Underflow Interrupt Flag */
\r
1811 #define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
\r
1812 #define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
\r
1813 #define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1814 #define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */
\r
1815 #define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */
\r
1816 #define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
\r
1817 #define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
\r
1818 #define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1819 #define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */
\r
1820 #define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */
\r
1821 #define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
\r
1822 #define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
\r
1823 #define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1824 #define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */
\r
1825 #define ADC_IF_VREFOV (0x1UL << 24) /**< VREF OverVoltage Interrupt Flag */
\r
1826 #define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
\r
1827 #define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
\r
1828 #define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1829 #define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */
\r
1830 #define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */
\r
1831 #define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
\r
1832 #define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
\r
1833 #define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
\r
1834 #define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */
\r
1836 /* Bit fields for ADC IFS */
\r
1837 #define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
\r
1838 #define _ADC_IFS_MASK 0x03030F00UL /**< Mask for ADC_IFS */
\r
1839 #define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */
\r
1840 #define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
1841 #define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
1842 #define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1843 #define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1844 #define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */
\r
1845 #define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
1846 #define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
1847 #define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1848 #define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1849 #define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */
\r
1850 #define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
\r
1851 #define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
\r
1852 #define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1853 #define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1854 #define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */
\r
1855 #define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
\r
1856 #define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
\r
1857 #define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1858 #define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1859 #define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */
\r
1860 #define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
\r
1861 #define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
\r
1862 #define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1863 #define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1864 #define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */
\r
1865 #define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
\r
1866 #define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
\r
1867 #define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1868 #define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1869 #define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */
\r
1870 #define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
\r
1871 #define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
\r
1872 #define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1873 #define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1874 #define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */
\r
1875 #define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
\r
1876 #define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
\r
1877 #define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
\r
1878 #define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */
\r
1880 /* Bit fields for ADC IFC */
\r
1881 #define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
\r
1882 #define _ADC_IFC_MASK 0x03030F00UL /**< Mask for ADC_IFC */
\r
1883 #define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */
\r
1884 #define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
1885 #define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
1886 #define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1887 #define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1888 #define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */
\r
1889 #define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
1890 #define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
1891 #define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1892 #define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1893 #define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */
\r
1894 #define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
\r
1895 #define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
\r
1896 #define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1897 #define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1898 #define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */
\r
1899 #define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
\r
1900 #define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
\r
1901 #define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1902 #define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1903 #define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */
\r
1904 #define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
\r
1905 #define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
\r
1906 #define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1907 #define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1908 #define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */
\r
1909 #define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
\r
1910 #define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
\r
1911 #define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1912 #define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1913 #define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */
\r
1914 #define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
\r
1915 #define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
\r
1916 #define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1917 #define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1918 #define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */
\r
1919 #define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
\r
1920 #define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
\r
1921 #define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
\r
1922 #define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */
\r
1924 /* Bit fields for ADC IEN */
\r
1925 #define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
\r
1926 #define _ADC_IEN_MASK 0x03030F03UL /**< Mask for ADC_IEN */
\r
1927 #define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */
\r
1928 #define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
\r
1929 #define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
\r
1930 #define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1931 #define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1932 #define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */
\r
1933 #define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
\r
1934 #define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
\r
1935 #define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1936 #define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1937 #define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */
\r
1938 #define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
\r
1939 #define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
\r
1940 #define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1941 #define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1942 #define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */
\r
1943 #define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
\r
1944 #define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
\r
1945 #define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1946 #define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1947 #define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */
\r
1948 #define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */
\r
1949 #define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */
\r
1950 #define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1951 #define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1952 #define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */
\r
1953 #define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */
\r
1954 #define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */
\r
1955 #define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1956 #define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1957 #define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */
\r
1958 #define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */
\r
1959 #define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */
\r
1960 #define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1961 #define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1962 #define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */
\r
1963 #define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */
\r
1964 #define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */
\r
1965 #define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1966 #define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1967 #define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */
\r
1968 #define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */
\r
1969 #define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */
\r
1970 #define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1971 #define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1972 #define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */
\r
1973 #define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */
\r
1974 #define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */
\r
1975 #define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
\r
1976 #define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */
\r
1978 /* Bit fields for ADC SINGLEDATA */
\r
1979 #define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
\r
1980 #define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
\r
1981 #define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
\r
1982 #define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
\r
1983 #define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
\r
1984 #define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
\r
1986 /* Bit fields for ADC SCANDATA */
\r
1987 #define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
\r
1988 #define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
\r
1989 #define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
\r
1990 #define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
\r
1991 #define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
\r
1992 #define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
\r
1994 /* Bit fields for ADC SINGLEDATAP */
\r
1995 #define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
\r
1996 #define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
\r
1997 #define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
\r
1998 #define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
\r
1999 #define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
\r
2000 #define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
\r
2002 /* Bit fields for ADC SCANDATAP */
\r
2003 #define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
\r
2004 #define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
\r
2005 #define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
\r
2006 #define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
\r
2007 #define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
\r
2008 #define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
\r
2010 /* Bit fields for ADC SCANDATAX */
\r
2011 #define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */
\r
2012 #define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */
\r
2013 #define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
\r
2014 #define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */
\r
2015 #define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */
\r
2016 #define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
\r
2017 #define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */
\r
2018 #define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */
\r
2019 #define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */
\r
2020 #define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */
\r
2022 /* Bit fields for ADC SCANDATAXP */
\r
2023 #define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */
\r
2024 #define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */
\r
2025 #define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
\r
2026 #define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */
\r
2027 #define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */
\r
2028 #define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
\r
2029 #define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */
\r
2030 #define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */
\r
2031 #define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */
\r
2032 #define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */
\r
2034 /* Bit fields for ADC APORTREQ */
\r
2035 #define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */
\r
2036 #define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */
\r
2037 #define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */
\r
2038 #define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */
\r
2039 #define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */
\r
2040 #define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2041 #define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2042 #define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */
\r
2043 #define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */
\r
2044 #define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */
\r
2045 #define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2046 #define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2047 #define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */
\r
2048 #define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */
\r
2049 #define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */
\r
2050 #define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2051 #define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2052 #define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
\r
2053 #define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */
\r
2054 #define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */
\r
2055 #define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2056 #define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2057 #define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */
\r
2058 #define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */
\r
2059 #define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */
\r
2060 #define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2061 #define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2062 #define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */
\r
2063 #define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */
\r
2064 #define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */
\r
2065 #define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2066 #define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2067 #define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */
\r
2068 #define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */
\r
2069 #define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */
\r
2070 #define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2071 #define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2072 #define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */
\r
2073 #define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */
\r
2074 #define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */
\r
2075 #define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2076 #define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2077 #define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */
\r
2078 #define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */
\r
2079 #define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */
\r
2080 #define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2081 #define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2082 #define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */
\r
2083 #define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */
\r
2084 #define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */
\r
2085 #define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */
\r
2086 #define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */
\r
2088 /* Bit fields for ADC APORTCONFLICT */
\r
2089 #define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */
\r
2090 #define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */
\r
2091 #define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */
\r
2092 #define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */
\r
2093 #define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */
\r
2094 #define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2095 #define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2096 #define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */
\r
2097 #define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */
\r
2098 #define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */
\r
2099 #define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2100 #define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2101 #define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
\r
2102 #define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */
\r
2103 #define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */
\r
2104 #define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2105 #define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2106 #define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
\r
2107 #define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */
\r
2108 #define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */
\r
2109 #define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2110 #define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2111 #define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */
\r
2112 #define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */
\r
2113 #define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */
\r
2114 #define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2115 #define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2116 #define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */
\r
2117 #define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */
\r
2118 #define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */
\r
2119 #define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2120 #define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2121 #define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */
\r
2122 #define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */
\r
2123 #define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */
\r
2124 #define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2125 #define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2126 #define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */
\r
2127 #define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */
\r
2128 #define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */
\r
2129 #define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2130 #define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2131 #define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */
\r
2132 #define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */
\r
2133 #define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */
\r
2134 #define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2135 #define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2136 #define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */
\r
2137 #define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */
\r
2138 #define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */
\r
2139 #define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */
\r
2140 #define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */
\r
2142 /* Bit fields for ADC SINGLEFIFOCOUNT */
\r
2143 #define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */
\r
2144 #define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */
\r
2145 #define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */
\r
2146 #define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */
\r
2147 #define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */
\r
2148 #define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */
\r
2150 /* Bit fields for ADC SCANFIFOCOUNT */
\r
2151 #define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */
\r
2152 #define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */
\r
2153 #define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */
\r
2154 #define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */
\r
2155 #define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */
\r
2156 #define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */
\r
2158 /* Bit fields for ADC SINGLEFIFOCLEAR */
\r
2159 #define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */
\r
2160 #define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */
\r
2161 #define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */
\r
2162 #define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */
\r
2163 #define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */
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2164 #define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */
\r
2165 #define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */
\r
2167 /* Bit fields for ADC SCANFIFOCLEAR */
\r
2168 #define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */
\r
2169 #define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */
\r
2170 #define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */
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2171 #define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */
\r
2172 #define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */
\r
2173 #define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */
\r
2174 #define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */
\r
2176 /* Bit fields for ADC APORTMASTERDIS */
\r
2177 #define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */
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2178 #define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */
\r
2179 #define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */
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2180 #define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */
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2181 #define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */
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2182 #define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
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2183 #define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2184 #define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */
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2185 #define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */
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2186 #define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */
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2187 #define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
\r
2188 #define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2189 #define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */
\r
2190 #define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */
\r
2191 #define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */
\r
2192 #define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
\r
2193 #define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2194 #define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */
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2195 #define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */
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2196 #define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */
\r
2197 #define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
\r
2198 #define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2199 #define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */
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2200 #define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */
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2201 #define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */
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2202 #define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
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2203 #define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2204 #define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */
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2205 #define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */
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2206 #define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */
\r
2207 #define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
\r
2208 #define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2209 #define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */
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2210 #define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */
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2211 #define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */
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2212 #define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
\r
2213 #define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2214 #define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */
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2215 #define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */
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2216 #define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */
\r
2217 #define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */
\r
2218 #define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */
\r
2220 /** @} End of group EFM32PG1B_ADC */
\r
2221 /** @} End of group Parts */
\r
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