1 /**************************************************************************//**
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2 * @file efm32pg1b_emu.h
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3 * @brief EFM32PG1B_EMU register and bit field definitions
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5 ******************************************************************************
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7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
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8 ******************************************************************************
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10 * Permission is granted to anyone to use this software for any purpose,
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11 * including commercial applications, and to alter it and redistribute it
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12 * freely, subject to the following restrictions:
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14 * 1. The origin of this software must not be misrepresented; you must not
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15 * claim that you wrote the original software.@n
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16 * 2. Altered source versions must be plainly marked as such, and must not be
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17 * misrepresented as being the original software.@n
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18 * 3. This notice may not be removed or altered from any source distribution.
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20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
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21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
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22 * providing the Software "AS IS", with no express or implied warranties of any
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23 * kind, including, but not limited to, any implied warranties of
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24 * merchantability or fitness for any particular purpose or warranties against
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25 * infringement of any proprietary rights of a third party.
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27 * Silicon Laboratories, Inc. will not be liable for any consequential,
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28 * incidental, or special damages, or any other relief, or for any claim by
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29 * any third party, arising from your use of this Software.
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31 *****************************************************************************/
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32 /**************************************************************************//**
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35 ******************************************************************************/
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36 /**************************************************************************//**
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37 * @defgroup EFM32PG1B_EMU
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39 * @brief EFM32PG1B_EMU Register Declaration
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40 *****************************************************************************/
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43 __IO uint32_t CTRL; /**< Control Register */
\r
44 __I uint32_t STATUS; /**< Status Register */
\r
45 __IO uint32_t LOCK; /**< Configuration Lock Register */
\r
46 __IO uint32_t RAM0CTRL; /**< Memory Control Register */
\r
47 __IO uint32_t CMD; /**< Command Register */
\r
48 __IO uint32_t PERACTCONF; /**< Peripheral to Peripheral Activation Clock Configuration */
\r
49 __IO uint32_t EM4CTRL; /**< EM4 Control Register */
\r
50 __IO uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */
\r
51 __I uint32_t TEMP; /**< Value of last temperature measurement */
\r
52 __I uint32_t IF; /**< Interrupt Flag Register */
\r
53 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
\r
54 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
\r
55 __IO uint32_t IEN; /**< Interrupt Enable Register */
\r
56 __IO uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
\r
57 __IO uint32_t PWRCFG; /**< Power Configuration Register. */
\r
58 __IO uint32_t PWRCTRL; /**< Power Control Register. */
\r
59 __IO uint32_t DCDCCTRL; /**< DCDC Control */
\r
61 uint32_t RESERVED0[2]; /**< Reserved for future use **/
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62 __IO uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
\r
63 __IO uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
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64 __IO uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
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66 uint32_t RESERVED1[1]; /**< Reserved for future use **/
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67 __IO uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
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68 __IO uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */
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69 __IO uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
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71 uint32_t RESERVED2[1]; /**< Reserved for future use **/
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72 __IO uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
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73 __IO uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
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75 uint32_t RESERVED3[1]; /**< Reserved for future use **/
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76 __I uint32_t DCDCSYNC; /**< DCDC Read Status Register */
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78 uint32_t RESERVED4[5]; /**< Reserved for future use **/
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79 __IO uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
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80 __IO uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
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81 __IO uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
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82 __IO uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
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83 } EMU_TypeDef; /** @} */
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85 /**************************************************************************//**
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86 * @defgroup EFM32PG1B_EMU_BitFields
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88 *****************************************************************************/
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90 /* Bit fields for EMU CTRL */
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91 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
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92 #define _EMU_CTRL_MASK 0x00000002UL /**< Mask for EMU_CTRL */
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93 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
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94 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
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95 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
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96 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
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97 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
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99 /* Bit fields for EMU STATUS */
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100 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
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101 #define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */
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102 #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */
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103 #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
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104 #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
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105 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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106 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
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107 #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */
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108 #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
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109 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
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110 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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111 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
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112 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */
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113 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
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114 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
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115 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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116 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
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117 #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */
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118 #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
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119 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
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120 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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121 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
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122 #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */
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123 #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
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124 #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
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125 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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126 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
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127 #define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */
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128 #define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
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129 #define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
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130 #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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131 #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */
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132 #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */
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133 #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */
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134 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */
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135 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
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136 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */
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137 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */
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138 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */
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139 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */
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140 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */
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142 /* Bit fields for EMU LOCK */
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143 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
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144 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
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145 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
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146 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
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147 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
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148 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
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149 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
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150 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
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151 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
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152 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
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153 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
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154 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
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155 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
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156 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
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158 /* Bit fields for EMU RAM0CTRL */
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159 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */
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160 #define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */
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161 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
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162 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */
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163 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */
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164 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */
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165 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */
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166 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */
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167 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */
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168 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */
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169 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
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170 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */
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171 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */
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172 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */
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173 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */
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174 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */
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176 /* Bit fields for EMU CMD */
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177 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
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178 #define _EMU_CMD_MASK 0x00000001UL /**< Mask for EMU_CMD */
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179 #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */
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180 #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */
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181 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
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182 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
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183 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
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185 /* Bit fields for EMU PERACTCONF */
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186 #define _EMU_PERACTCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PERACTCONF */
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187 #define _EMU_PERACTCONF_MASK 0x00000001UL /**< Mask for EMU_PERACTCONF */
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188 #define EMU_PERACTCONF_RACPER (0x1UL << 0) /**< Enable PER clock when RAC is activated */
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189 #define _EMU_PERACTCONF_RACPER_SHIFT 0 /**< Shift value for EMU_RACPER */
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190 #define _EMU_PERACTCONF_RACPER_MASK 0x1UL /**< Bit mask for EMU_RACPER */
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191 #define _EMU_PERACTCONF_RACPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PERACTCONF */
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192 #define EMU_PERACTCONF_RACPER_DEFAULT (_EMU_PERACTCONF_RACPER_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PERACTCONF */
\r
194 /* Bit fields for EMU EM4CTRL */
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195 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
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196 #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */
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197 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */
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198 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */
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199 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */
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200 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
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201 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */
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202 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */
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203 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
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204 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
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205 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
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206 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */
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207 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
\r
208 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
\r
209 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
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210 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
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211 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */
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212 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
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213 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
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214 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
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215 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
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216 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */
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217 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
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218 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
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219 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
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220 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
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221 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
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222 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
\r
223 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
\r
224 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
\r
225 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
\r
226 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
\r
227 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
\r
228 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
\r
229 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
\r
230 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
\r
231 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */
\r
232 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */
\r
233 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
\r
234 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
\r
236 /* Bit fields for EMU TEMPLIMITS */
\r
237 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */
\r
238 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */
\r
239 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
\r
240 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */
\r
241 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
\r
242 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
\r
243 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */
\r
244 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
\r
245 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
\r
246 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
\r
247 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temerature */
\r
248 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
\r
249 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
\r
250 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
\r
251 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
\r
253 /* Bit fields for EMU TEMP */
\r
254 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
\r
255 #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */
\r
256 #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */
\r
257 #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */
\r
258 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
\r
259 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
\r
261 /* Bit fields for EMU IF */
\r
262 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
\r
263 #define _EMU_IF_MASK 0xE11FC0FFUL /**< Mask for EMU_IF */
\r
264 #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */
\r
265 #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
\r
266 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
\r
267 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
268 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
\r
269 #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */
\r
270 #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
\r
271 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
\r
272 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
273 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */
\r
274 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */
\r
275 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
\r
276 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
\r
277 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
278 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */
\r
279 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */
\r
280 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
\r
281 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
\r
282 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
283 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */
\r
284 #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */
\r
285 #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
\r
286 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
\r
287 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
288 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */
\r
289 #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */
\r
290 #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
\r
291 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
\r
292 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
293 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */
\r
294 #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */
\r
295 #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
\r
296 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
\r
297 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
298 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */
\r
299 #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */
\r
300 #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
\r
301 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
\r
302 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
303 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */
\r
304 #define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */
\r
305 #define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
\r
306 #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
\r
307 #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
308 #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */
\r
309 #define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */
\r
310 #define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
\r
311 #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
\r
312 #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
313 #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
\r
314 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */
\r
315 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
\r
316 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
\r
317 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
318 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
\r
319 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */
\r
320 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
\r
321 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
\r
322 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
323 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
\r
324 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */
\r
325 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
\r
326 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
\r
327 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
328 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
\r
329 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */
\r
330 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
\r
331 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
\r
332 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
333 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
\r
334 #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */
\r
335 #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
\r
336 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
\r
337 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
338 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
\r
339 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */
\r
340 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
\r
341 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
\r
342 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
343 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
\r
344 #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */
\r
345 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
\r
346 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
\r
347 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
348 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
\r
349 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */
\r
350 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
\r
351 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
\r
352 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
353 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
\r
354 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */
\r
355 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
\r
356 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
\r
357 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
\r
358 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
\r
360 /* Bit fields for EMU IFS */
\r
361 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
\r
362 #define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */
\r
363 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */
\r
364 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
\r
365 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
\r
366 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
367 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
\r
368 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */
\r
369 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
\r
370 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
\r
371 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
372 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */
\r
373 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */
\r
374 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
\r
375 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
\r
376 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
377 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */
\r
378 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */
\r
379 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
\r
380 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
\r
381 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
382 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */
\r
383 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */
\r
384 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
\r
385 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
\r
386 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
387 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */
\r
388 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */
\r
389 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
\r
390 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
\r
391 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
392 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */
\r
393 #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */
\r
394 #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
\r
395 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
\r
396 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
397 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */
\r
398 #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */
\r
399 #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
\r
400 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
\r
401 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
402 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */
\r
403 #define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */
\r
404 #define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */
\r
405 #define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */
\r
406 #define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
407 #define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */
\r
408 #define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */
\r
409 #define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */
\r
410 #define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */
\r
411 #define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
412 #define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */
\r
413 #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */
\r
414 #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
\r
415 #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
\r
416 #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
417 #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */
\r
418 #define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */
\r
419 #define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
\r
420 #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
\r
421 #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
422 #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */
\r
423 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
\r
424 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
\r
425 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
\r
426 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
427 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
\r
428 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
\r
429 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
\r
430 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
\r
431 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
432 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
\r
433 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */
\r
434 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
\r
435 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
\r
436 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
437 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */
\r
438 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */
\r
439 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
\r
440 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
\r
441 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
442 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */
\r
443 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */
\r
444 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
\r
445 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
\r
446 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
447 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */
\r
448 #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */
\r
449 #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
\r
450 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
\r
451 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
452 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */
\r
453 #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */
\r
454 #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
\r
455 #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
\r
456 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
457 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */
\r
458 #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */
\r
459 #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
\r
460 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
\r
461 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
462 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */
\r
463 #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */
\r
464 #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
\r
465 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
\r
466 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
\r
467 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */
\r
469 /* Bit fields for EMU IFC */
\r
470 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
\r
471 #define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */
\r
472 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */
\r
473 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
\r
474 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
\r
475 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
476 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
\r
477 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */
\r
478 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
\r
479 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
\r
480 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
481 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */
\r
482 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */
\r
483 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
\r
484 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
\r
485 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
486 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */
\r
487 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */
\r
488 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
\r
489 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
\r
490 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
491 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */
\r
492 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */
\r
493 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
\r
494 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
\r
495 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
496 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */
\r
497 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */
\r
498 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
\r
499 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
\r
500 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
501 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */
\r
502 #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */
\r
503 #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
\r
504 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
\r
505 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
506 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */
\r
507 #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */
\r
508 #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
\r
509 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
\r
510 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
511 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */
\r
512 #define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */
\r
513 #define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */
\r
514 #define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */
\r
515 #define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
516 #define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */
\r
517 #define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */
\r
518 #define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */
\r
519 #define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */
\r
520 #define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
521 #define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */
\r
522 #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */
\r
523 #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
\r
524 #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
\r
525 #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
526 #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */
\r
527 #define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */
\r
528 #define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
\r
529 #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
\r
530 #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
531 #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */
\r
532 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
\r
533 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
\r
534 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
\r
535 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
536 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
\r
537 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
\r
538 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
\r
539 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
\r
540 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
541 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
\r
542 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */
\r
543 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
\r
544 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
\r
545 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
546 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */
\r
547 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */
\r
548 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
\r
549 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
\r
550 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
551 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */
\r
552 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */
\r
553 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
\r
554 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
\r
555 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
556 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */
\r
557 #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */
\r
558 #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
\r
559 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
\r
560 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
561 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */
\r
562 #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */
\r
563 #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
\r
564 #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
\r
565 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
566 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */
\r
567 #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */
\r
568 #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
\r
569 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
\r
570 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
571 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */
\r
572 #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */
\r
573 #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
\r
574 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
\r
575 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
\r
576 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */
\r
578 /* Bit fields for EMU IEN */
\r
579 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
\r
580 #define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */
\r
581 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */
\r
582 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
\r
583 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
\r
584 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
585 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
\r
586 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */
\r
587 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
\r
588 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
\r
589 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
590 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */
\r
591 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */
\r
592 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
\r
593 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
\r
594 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
595 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */
\r
596 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */
\r
597 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
\r
598 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
\r
599 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
600 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */
\r
601 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */
\r
602 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
\r
603 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
\r
604 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
605 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */
\r
606 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */
\r
607 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
\r
608 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
\r
609 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
610 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */
\r
611 #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */
\r
612 #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
\r
613 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
\r
614 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
615 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */
\r
616 #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */
\r
617 #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
\r
618 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
\r
619 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
620 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */
\r
621 #define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */
\r
622 #define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */
\r
623 #define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */
\r
624 #define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
625 #define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */
\r
626 #define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */
\r
627 #define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */
\r
628 #define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */
\r
629 #define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
630 #define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */
\r
631 #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */
\r
632 #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
\r
633 #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
\r
634 #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
635 #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */
\r
636 #define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */
\r
637 #define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
\r
638 #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
\r
639 #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
640 #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */
\r
641 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */
\r
642 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
\r
643 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
\r
644 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
645 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
\r
646 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */
\r
647 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
\r
648 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
\r
649 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
650 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
\r
651 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */
\r
652 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
\r
653 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
\r
654 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
655 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */
\r
656 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */
\r
657 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
\r
658 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
\r
659 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
660 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */
\r
661 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */
\r
662 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
\r
663 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
\r
664 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
665 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */
\r
666 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */
\r
667 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
\r
668 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
\r
669 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
670 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
\r
671 #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */
\r
672 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
\r
673 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
\r
674 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
675 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
\r
676 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */
\r
677 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
\r
678 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
\r
679 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
680 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
\r
681 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */
\r
682 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
\r
683 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
\r
684 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
\r
685 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
\r
687 /* Bit fields for EMU PWRLOCK */
\r
688 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */
\r
689 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */
\r
690 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
\r
691 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
\r
692 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
\r
693 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
\r
694 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
\r
695 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
\r
696 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
\r
697 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
\r
698 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
\r
699 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
\r
700 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
\r
701 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
\r
703 /* Bit fields for EMU PWRCFG */
\r
704 #define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */
\r
705 #define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */
\r
706 #define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */
\r
707 #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */
\r
708 #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */
\r
709 #define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL /**< Mode STARTUP for EMU_PWRCFG */
\r
710 #define _EMU_PWRCFG_PWRCFG_NODCDC 0x00000001UL /**< Mode NODCDC for EMU_PWRCFG */
\r
711 #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */
\r
712 #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */
\r
713 #define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0) /**< Shifted mode STARTUP for EMU_PWRCFG */
\r
714 #define EMU_PWRCFG_PWRCFG_NODCDC (_EMU_PWRCFG_PWRCFG_NODCDC << 0) /**< Shifted mode NODCDC for EMU_PWRCFG */
\r
715 #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */
\r
717 /* Bit fields for EMU PWRCTRL */
\r
718 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */
\r
719 #define _EMU_PWRCTRL_MASK 0x00000020UL /**< Mask for EMU_PWRCTRL */
\r
720 #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */
\r
721 #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */
\r
722 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */
\r
723 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
\r
724 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
\r
725 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
\r
726 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
\r
727 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
\r
728 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
\r
730 /* Bit fields for EMU DCDCCTRL */
\r
731 #define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL /**< Default value for EMU_DCDCCTRL */
\r
732 #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */
\r
733 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */
\r
734 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */
\r
735 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCTRL */
\r
736 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */
\r
737 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */
\r
738 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */
\r
739 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */
\r
740 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
\r
741 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */
\r
742 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
\r
743 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
\r
744 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */
\r
745 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< Reserved for internal use. Do not change. */
\r
746 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */
\r
747 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */
\r
748 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
\r
749 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
\r
750 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< Reserved for internal use. Do not change. */
\r
751 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */
\r
752 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */
\r
753 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
\r
754 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
\r
756 /* Bit fields for EMU DCDCMISCCTRL */
\r
757 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */
\r
758 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */
\r
759 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */
\r
760 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
\r
761 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
\r
762 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
763 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
764 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */
\r
765 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */
\r
766 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
767 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
768 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */
\r
769 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */
\r
770 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
771 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
772 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */
\r
773 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */
\r
774 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
775 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
776 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */
\r
777 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */
\r
778 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
779 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
780 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */
\r
781 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */
\r
782 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
783 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
784 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28 /**< Shift value for EMU_LPCMPBIAS */
\r
785 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIAS */
\r
786 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
\r
787 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
\r
788 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
\r
789 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
\r
790 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
\r
791 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
\r
792 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
\r
793 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
\r
794 #define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
\r
795 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
\r
797 /* Bit fields for EMU DCDCZDETCTRL */
\r
798 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL /**< Default value for EMU_DCDCZDETCTRL */
\r
799 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */
\r
800 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */
\r
801 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */
\r
802 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
\r
803 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
\r
804 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */
\r
805 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */
\r
806 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
\r
807 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
\r
809 /* Bit fields for EMU DCDCCLIMCTRL */
\r
810 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL /**< Default value for EMU_DCDCCLIMCTRL */
\r
811 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */
\r
812 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */
\r
813 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */
\r
814 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
\r
815 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
\r
816 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */
\r
817 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */
\r
818 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */
\r
819 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
\r
820 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
\r
822 /* Bit fields for EMU DCDCLNVCTRL */
\r
823 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */
\r
824 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */
\r
825 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */
\r
826 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */
\r
827 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */
\r
828 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
\r
829 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */
\r
830 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */
\r
831 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
\r
832 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
\r
833 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
\r
834 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */
\r
835 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */
\r
836 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
\r
837 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
\r
839 /* Bit fields for EMU DCDCTIMING */
\r
840 #define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL /**< Default value for EMU_DCDCTIMING */
\r
841 #define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL /**< Mask for EMU_DCDCTIMING */
\r
842 #define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0 /**< Shift value for EMU_LPINITWAIT */
\r
843 #define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */
\r
844 #define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
\r
845 #define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
\r
846 #define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN mode precharge enable */
\r
847 #define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */
\r
848 #define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */
\r
849 #define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */
\r
850 #define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
\r
851 #define _EMU_DCDCTIMING_LNWAIT_SHIFT 12 /**< Shift value for EMU_LNWAIT */
\r
852 #define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL /**< Bit mask for EMU_LNWAIT */
\r
853 #define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL /**< Mode DEFAULT for EMU_DCDCTIMING */
\r
854 #define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
\r
855 #define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20 /**< Shift value for EMU_BYPWAIT */
\r
856 #define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL /**< Bit mask for EMU_BYPWAIT */
\r
857 #define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
\r
858 #define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
\r
859 #define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29 /**< Shift value for EMU_DUTYSCALE */
\r
860 #define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL /**< Bit mask for EMU_DUTYSCALE */
\r
861 #define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCTIMING */
\r
862 #define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
\r
864 /* Bit fields for EMU DCDCLPVCTRL */
\r
865 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
\r
866 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
\r
867 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */
\r
868 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
\r
869 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
\r
870 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
\r
871 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */
\r
872 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */
\r
873 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
\r
874 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
\r
875 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
\r
876 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */
\r
877 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */
\r
878 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
\r
879 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
\r
881 /* Bit fields for EMU DCDCLPCTRL */
\r
882 #define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL /**< Default value for EMU_DCDCLPCTRL */
\r
883 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */
\r
884 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSEL */
\r
885 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */
\r
886 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
\r
887 #define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
\r
888 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< Lp mode duty cycling enable */
\r
889 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
\r
890 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
\r
891 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
\r
892 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
\r
893 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */
\r
894 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */
\r
895 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
\r
896 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
\r
898 /* Bit fields for EMU DCDCLNFREQCTRL */
\r
899 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */
\r
900 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */
\r
901 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */
\r
902 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */
\r
903 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
\r
904 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
\r
905 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */
\r
906 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */
\r
907 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
\r
908 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
\r
910 /* Bit fields for EMU DCDCSYNC */
\r
911 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
\r
912 #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
\r
913 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */
\r
914 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
\r
915 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
\r
916 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
\r
917 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
\r
919 /* Bit fields for EMU VMONAVDDCTRL */
\r
920 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */
\r
921 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */
\r
922 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */
\r
923 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
\r
924 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
\r
925 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
926 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
927 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
\r
928 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
\r
929 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
\r
930 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
931 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
932 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
\r
933 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
\r
934 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
\r
935 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
936 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
937 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */
\r
938 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */
\r
939 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
940 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
941 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */
\r
942 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */
\r
943 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
944 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
945 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */
\r
946 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */
\r
947 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
948 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
949 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */
\r
950 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */
\r
951 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
\r
952 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
\r
954 /* Bit fields for EMU VMONALTAVDDCTRL */
\r
955 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */
\r
956 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */
\r
957 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */
\r
958 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
\r
959 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
\r
960 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
961 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
962 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
\r
963 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
\r
964 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
\r
965 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
966 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
967 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
\r
968 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
\r
969 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
\r
970 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
971 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
972 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
\r
973 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
\r
974 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
975 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
976 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
\r
977 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
\r
978 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
979 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
\r
981 /* Bit fields for EMU VMONDVDDCTRL */
\r
982 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */
\r
983 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */
\r
984 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */
\r
985 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
\r
986 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
\r
987 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
\r
988 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
\r
989 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
\r
990 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
\r
991 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
\r
992 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
\r
993 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
\r
994 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
\r
995 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
\r
996 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
\r
997 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
\r
998 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
\r
999 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
\r
1000 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
\r
1001 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
\r
1002 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
\r
1003 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
\r
1004 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
\r
1005 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
\r
1006 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
\r
1008 /* Bit fields for EMU VMONIO0CTRL */
\r
1009 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */
\r
1010 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */
\r
1011 #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */
\r
1012 #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
\r
1013 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
\r
1014 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
\r
1015 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
\r
1016 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
\r
1017 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
\r
1018 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
\r
1019 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
\r
1020 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
\r
1021 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
\r
1022 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
\r
1023 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
\r
1024 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
\r
1025 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
\r
1026 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */
\r
1027 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
\r
1028 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
\r
1029 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
\r
1030 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
\r
1031 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
\r
1032 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
\r
1033 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
\r
1034 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
\r
1035 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
\r
1036 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
\r
1037 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
\r
1038 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
\r
1040 /** @} End of group EFM32PG1B_EMU */
\r
1041 /** @} End of group Parts */
\r
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